Overview
The following information applies to both the Chip and Core versions of this 65xx brand microprocessor family member.
WDC's high volume production proven 65xx brand microprocessor family of manually designed GDSII hard cores are highly optimized cores that are small and low power and therefore an excellent choice for low power System-on-Chip (SoC) ASIC microcontroller designs. These static cores support a wide range of applications from radiation resistant hi-rel applications such as medical implantable life-support devices to ultra high volume consumer devices.
The WDC CMOS W65C51S Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between microprocessor based systems and serial communication data sets and modems.
The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits. The Transmitter baud rate can be selected under program control to be 1 of 15 different rates from 50 to 19,200 baud, or at 1/16 times an external clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate or at 1/16 times the external clock rate. The ACIA has programmable word lengths of 5, 6, 7 or 8 bits; even, odd or no parity 1, 1½ or 2 stop bits.
Learn more about UART IP core
With the increasing number of high-profile data and privacy breaches in the Internet of Things (IoT) systems, businesses and consumers have a greater awareness of the need for security when buying connected products.
The universal asynchronous receiver/transmitter (UART) is an old friend to embedded systems engineers. It's probably the first communications protocol that we learn in college. In this article, we will design our very own UART using MyHDL.
Post-quantum cryptography (PQC) is moving from theory to engineering reality. With NIST-standardized algorithms ML-KEM (FIPS 203) and ML-DSA (FIPS 204) now finalized, FPGA developers face a practical challenge: How to integrate these algorithms efficiently on resource-constrained hardware?
In today’s connected world, where data is a crucial asset in SoCs, Part V of our series explores how to protect and encrypt data, whether at rest, in transit, or in use building on our earlier blog posts of the series: Essential security features for digital designers, key management, secure boot, and runtime integrity.
Most foundries provide GPIO libraries to their fabless customers. These libraries contain different elements like supply/ground pads, analog I/Os, digital I/Os, corner cells, filler cells, power-on-reset circuits. Frequently the foundry includes cells for different voltage domains. In 40nm CMOS the IC designer can use cells for 1.8V, 2.5V and 3.3V for instance.
Build safety-critical automotive, aeronautic, space and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire® FPGAs.
