Vendor: Agile Analog Category: DAC

8/10-bit Digital-to-Analog Converter

The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture.

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10 Bit View all specifications

Overview

The agileDAC GP is a digital-to-analog converter that uses a traditional capacitive DAC architecture. The agileDAC uses its own internal reference voltage. The architecture can achieve up to 10-bit resolution at sample rates up to 16 Msps.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key features

  • Resolution: 8bits /10bits
  • Sampling Rate (Fs): up to 16Msps
  • Output Signal Bandwidth: Typ Fs/2
  • Guaranteed monotonic
  • SFDR1: Typ -60dBc
  • INL: Max2 ±4LSB
  • DNL: Max2 ±2LSB
  • Conversion Time: Typ 2 cycles
  • Quiescent current3 (Iq):Typ 250uA
  • Customizable design for simple SoC integration
  • Integrated Calibration Mode

Block Diagram

agileDAC block diagram

Benefits

  • DFT/DFM
  • - AMBA-APB Interface to simply test and operation
  • - Built-in Trim and Calibration to facilitate process and/or manufacturing offsets to be adjusted

Applications

  • IoT, Security, Automotive, AI, SoCs, ASICs

What’s Included?

  • Datasheet
  • Testing and Integration Guide
  • Verilog Models
  • Floorplan (LEF)
  • Timing models (LIB)
  • Netlist (CDL)
  • Layout (GDS)
  • Physical Verification Report
  • Design Report

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
agileDAC
Vendor
Agile Analog
Type
Silicon IP

Analog

Resolution bits
10 Bit

Provider

Agile Analog
HQ: United Kingdom
Agile Analog is transforming the world of analog IP with Composa™, its innovative, configurable, multi-process analog IP technology. Headquartered in Cambridge, UK, with a growing number of partners and customers across the globe, Agile Analog has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications on almost any process from any foundry. The company provides a wide and ever expanding selection of analog IP and subsystems for power management, data conversion, IC health and monitoring, security and always-on domains. Agile Analog's novel approach utilises tried and tested analog circuits within its Composa library to create customised and verified analog IP solutions. This reduces the time to market and increases quality, helping to accelerate innovation in semiconductor design.
Contact Agile Analog

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 8/10-bit Digital-to-Analog Converter?

8/10-bit Digital-to-Analog Converter is a DAC IP core from Agile Analog listed on Semi IP Hub.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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