Vendor: Synopsys, Inc. Category: DSP Core

512-bit Vector DSP IP, Single Core

The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on…

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Overview

The ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on devices to automotive ADAS to communications and high-performance computing.

The VPX Family supports multiple vector lengths and core configurations:

128-bit vector word – VPX2 (single core), VPX2x2 (dual core)

256-bit vector word – VPX3 (single core), VPX3x2 (dual core)

512-bit vector word – VPX5 (single core), VPX5x2 (dual core), VPX5x4 (quad core)

VPX DSP processors feature a 4-way VLIW architecture optimally balanced to achieve high performance with low power consumption. Each VPX DSP core integrates a high-performance 32-bit scalar pipeline and a multi-slot vector processing unit supporting 8-bit, 16-bit, and 32-bit SIMD computations. Each VPX DSP core is capable of executing one scalar and three vector instructions per cycle. The VPX DSPs are supported by configurable instruction and data caches for scalar operations and vector closely-coupled memory (VCCM) with single cycle access for vector processing. Like all ARC processors, the VPX DSPs are highly scalable and configurable, enabling users to tailor them to meet specific performance-power-area (PPA) requirements.

Each VPX DSP core has up to three parallel floating-point processing pipelines, including two optional IEEE-754 compliant vector floating point units that support both full- (32-bit) and half- (16-bit) precision floating point operations. The VPX cores also have the option to add a dedicated vector floating point pipe that accelerates an extensive set of math functions including div, √x, 1/√x, sin(x), cos(x), log_2 (x), 2^x, and e^x.

To speed application software development, the VPX Family is supported by the vendor’s ARC MetaWare tools, which provide a comprehensive and vector-length agnostic software programming environment that enables code portability among all members of the VPX family. The tool suite includes an optimizing C/C++ vector compiler, debugger, instruction set simulator, as well as vector-based DSP, machine learning inference and linear algebra libraries.

Key features

  • Four-way VLIW combining scalar and vector operations
  • 128-bit, 256-bit and 512-bit vector word lengths
  • 8, 16, and 32-bit integer SIMD engines
  • IEEE 754-compliant vector floating point unit option offers single-precision or half-precision operations and advanced math functions
    • Dual vector floating point SIMD pipes
    • Hardware acceleration for math functions
  • Single- and multicore-configured offerings
  • ARC MetaWare tools including an auto vectorizing C/C++ compiler, debugger, simulator, vector DSP and vector linear algebra libraries, and neural network SDK

Block Diagram

dwc_arc_vpx5_dsp block diagram

Files

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Specifications

Identity

Part Number
dwc_arc_vpx5_dsp
Vendor
Synopsys, Inc.
Type
Silicon IP

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Contact Synopsys, Inc.

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Frequently asked questions about DSP Core IP cores

What is 512-bit Vector DSP IP, Single Core?

512-bit Vector DSP IP, Single Core is a DSP Core IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this DSP Core?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.

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