Vendor: Codasip Category: CPU

32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification

The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification.

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Overview

The L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering, this embedded processor is ideal either as a Main Controller or a Safety Island in a Functional Safety System.

It includes 2 instances of the L31 in a dual-core lockstep configuration along with Physical Memory Protection as a security feature.
 

L31AS is an in-order, 3-stage, single-issue RISC-V core targeted for automotive and other functional safety applications. It is based on the RV32IMC ISA. It includes physical memory protection.  

L31AS features separate Data and Instruction AHB-Lite interfaces, block-level gating in single-core configuration and performance counters. It uses the standard RISC-V debug specification with 4 debug triggers and Debug Memory Interface (DMI) as an APB interface that can be used to interface with external debuggers.  

Certified for Functional Safety

The L31AS core is certified by TÜV SÜD according to the requirements set forth in ISO26262 up to ASIL B. It is delivered with a safety pack including a safety manual and a safety case report. 

Software development

Using standard AMBA AHB Interface, L31AS can easily be connected to existing systems and interconnects. What is more, L31AS is designed to simplify software development, with essential features to support developers:  

  • Debug interface – using standard RISC-V Debug specification   
  • Instruction-accurate model – for fast execution of software, before hardware is available  
  • Cycle-accurate model – for software algorithm optimization, when time constraints require precise execution  
  • Full trace capability – in the cycle-accurate model, to hunt hard-to-find bugs  

Key features

  • Flexible use cases
    • Safety Island as a protected enclave of the device providing freedom of interface for the independent execution of safety-related application code. 
    • Controller, running the safety-related application code. 
  • Proven technology
    • Based on the L31 silicon-proven embedded processor 
    • State-of-the-art verification scheme brings quality and reliability 
  • State-of-the-art safety and security
    • Dual-core lockstep provides a robust and well trusted approach to building high-reliability systems and meeting the stringent safety requirements of critical applications 
    • ​L31AS increases security against certain threat scenarios and can help meet requirements for security certification 

Block Diagram

Codasip L31AS block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
Codasip L31AS
Vendor
Codasip

Provider

Codasip
HQ: Germany
With semiconductor scaling failing, it is becoming necessary to design specialised cores optimised to a particular workload. With its open and modular ISA, RISC-V is a good basis on which to build a domain-specific accelerator. Codasip’s family of RISC-V cores covers the range from simple embedded applications to application processors capable of running Linux. The cores offer a variety of different pipeline lengths and computational options. These cores can be supplied in standard off-the-shelf configurations or can be extended using the Codasip Studio tool to achieve your unique processing requirements. Codasip Studio – used to develop the Codasip RISC-V cores – allows hardware and software design kits to be automatically generated from a high-level processor description language. Codasip began operations as a spinout from the Brno University of Technology/Faculty of Information Technology in 2014 based on 10 years of research. Codasip is a founding member of the RISC-V International and was the first company to offer a commercial RISC-V IP core in 2015. Today in addition to the original R & D centre in Brno, Czech Republic, Codasip has design centres in France and the UK. Codasip has sales offices in Europe, North America, China, Japan and Korea.
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Frequently asked questions about CPU IP cores

What is 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification?

32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification is a CPU IP core from Codasip listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

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