Vendor: Codasip Category: CPU

32 bit - Compact RISC-V Processor Core

The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements.

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Overview

The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose registers.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.
 

Key features

  • 32-bit RISC-V core
  • RV32EMC instruction set
  • 16 general purpose registers
  • Either small sequential multiplier
  • 3-stage pipeline
  • RISC-V privilege mode support:
    • Machine
  • Standard RISC-V CLINT
    • Up to 256 sources
  • Wakeup interrupt controller
  • NMI
  • On-chip debugger
    • RISC-V Debug module
  • 2/4 pin JTAG
  • 2-8 breakpoints/watchpoints

Block Diagram

Codasip L11 block diagram

Benefits

  • Flexibility
    • Wide choice of configuration options.
  • Extensibility
    • Ability to create custom RISC-V extensions to optimise performance
    • Efficient architectural exploration of custom extensions with Studio
    • Automatic HDK and SDK generation from Studio
    • Rigorous verification of modified L11 core using UVM
  • Tensor Flow Lite Micro is supported
  •  

Applications

  • The L11 is aimed at low- to mid-range embedded applications such as IoT, intelligent sensors and wireless

What’s Included?

  • Human-readable and structured RTL in either:
    • Verilog
    • VHDL
    • System Verilog
  • Hardware development kit (HDK)
    • Synthesis scripts
    • Simulation testbenches
    • Debug support
  • Software development kit (SDK)
    • LLVM C-compiler
    • Assembler
    • Disassembler
    • Linker
    • Instruction-accurate simulator
    • Cycle-accurate simulator
    • Profiler
  • Option for extending L11
    • CodAL model for Codasip Studio

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Codasip L11
Vendor
Codasip

Provider

Codasip
HQ: Germany
With semiconductor scaling failing, it is becoming necessary to design specialised cores optimised to a particular workload. With its open and modular ISA, RISC-V is a good basis on which to build a domain-specific accelerator. Codasip’s family of RISC-V cores covers the range from simple embedded applications to application processors capable of running Linux. The cores offer a variety of different pipeline lengths and computational options. These cores can be supplied in standard off-the-shelf configurations or can be extended using the Codasip Studio tool to achieve your unique processing requirements. Codasip Studio – used to develop the Codasip RISC-V cores – allows hardware and software design kits to be automatically generated from a high-level processor description language. Codasip began operations as a spinout from the Brno University of Technology/Faculty of Information Technology in 2014 based on 10 years of research. Codasip is a founding member of the RISC-V International and was the first company to offer a commercial RISC-V IP core in 2015. Today in addition to the original R & D centre in Brno, Czech Republic, Codasip has design centres in France and the UK. Codasip has sales offices in Europe, North America, China, Japan and Korea.
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32 bit - Compact RISC-V Processor Core is a CPU IP core from Codasip listed on Semi IP Hub.

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