Vendor: NTLab Category: Single-Protocol PHY

2.4 Gbps LVDS transmitter

065TSMC_LVDS_07 is LVDS transmitter.

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TSMC 65nm GP Pre-Silicon View all specifications

Overview

065TSMC_LVDS_07 is LVDS transmitter. The interface to the core logic includes differential signal pins (INP and INN) to transmit data, and control pin EN to configure the state of the transmitter. EN pin enables of the TX LVDS, OEN pin selects Hi-Z state mode in which the output is disconnected. There are other two internal pins (VREF and IREF) to get voltage reference and current reference. OUTP and OUTN are complementary outputs to connect to the bonding pads.

Key features

  • TSMC CMOS 0.065 um
  • 2.5 V analog power supply
  • 2.5 V CMOS input logic signals
  • 2.4 Gbps (DDR MODE) switching rates
  • Conforms to TIA/EIA-644 LVDS standards
  • Temperature range: -40 °C to + 85 °C
  • Optimized for pad-limited layout design
  • Portable to other technologies (upon request)

Block Diagram

065TSMC_LVDS_07 block diagram

Applications

  • Point-to-point data transmission
  • Multidrop buses
  • Clock distribution
  • Backplane data transmission
  • Cable data transmission
  • Half-duplex or duplex data transmission

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 65nm GP Pre-Silicon

Specifications

Identity

Part Number
065TSMC_LVDS_07
Vendor
NTLab
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
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Frequently asked questions about Single-Protocol PHY IP

What is 2.4 Gbps LVDS transmitter?

2.4 Gbps LVDS transmitter is a Single-Protocol PHY IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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