16nA Resistive Current Bias Low Voltage (1.0V), Low Power (360nW @ 1.2V)
This macro-cell is a low power general purpose current bias generator core designed for SilTerra 0.18µm CL180G CMOS technology.
Overview
This macro-cell is a low power general purpose current bias generator core designed for SilTerra 0.18µm CL180G CMOS technology.
The circuit generates 7 × NMOS 16nA current branches and 1 × NMOS 8nA branch. The current bias is temperature compensated using the PTAT thermal coefficient (TC) of an integrated resistor.
The core is easily retargeted to any other CMOS technology due to high portability architecture.
Key features
- Low power current bias
- Low TC
- Ibias=15.5nA ±10% (without trimming)
- Current consumption around 300nA in active mode
- Flexible voltage operation: 1.0V–2.0V
- Enable control
- Indicative area: 0.0072mm2
Block Diagram
Applications
- Passive/active RFID tag ICs
- Battery powered equipment
- Energy Harvesting ICs
- Hearing Aids
What’s Included?
- Datasheet/Integration Guide
- HDL Model
- Flat GDSII database/LVS netlist
- Customer Support
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Silterra | 180nm | G | Silicon Proven |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Voltage Reference IP cores
What is 16nA Resistive Current Bias Low Voltage (1.0V), Low Power (360nW @ 1.2V)?
16nA Resistive Current Bias Low Voltage (1.0V), Low Power (360nW @ 1.2V) is a Voltage Reference IP core from Chipus Microelectronics listed on Semi IP Hub. It is listed with support for silterra Silicon Proven.
How should engineers evaluate this Voltage Reference?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Voltage Reference IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.