Vendor: NTLab Category: Single-Protocol PHY

1.25 Gbps LVDS IPs library

028TSMC_LVDS_01 is a library including: Transmitter LVDS driver (TX_LVDS); Receiver LVDS driver (RX_LVDS); Reduced range link rec…

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TSMC 28nm Pre-Silicon View all specifications

Overview

028TSMC_LVDS_01 is a library including:

  •  Transmitter LVDS driver (TX_LVDS);
  •  Receiver LVDS driver (RX_LVDS);
  •  Reduced range link receiver LVDS driver (RX_LVDS_R);
  •  Transceiver LVDS driver (RX_TX_LVDS);
  •  Reference current/voltage generators (RS_TOP);
  •  Bias block (LVDSBIAS8X) for 8 LVDS drivers

RX_TX_LVDS driver has five available operation modes: transmitter, receiver, transmitter half-duplex, receiver half-duplex and shutdown. The RS_TOP block is intended to output reference currents and voltage for RX_LVDS, RX_LVDS_R, TX_LVDS and TX_RX_LVDS drivers as well as for bias block. Composing of LVDS library components allows to design a device with up to 16 pairs of data channels and 2 pairs of synchronization channels.

Key features

  • TSMC 28nm CMOS
  • TIA/EIA-644 LVDS standards without hysteresis
  • Data transfer rate: 1250Mbps
  • 1.8V IO voltage supply
  • 0.9V core voltage supply
  • 0.9V CMOS input/output logic control signals
  • 0.9V/1.8V level shifters

Block Diagram

028TSMC_LVDS_01 block diagram

Applications

  • Point-to-point data transmission
  • Multidrop buses
  • Clock distribution
  • Backplane receiver
  • Backplane data transmission
  • Cable data transmission

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentationn

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm Pre-Silicon

Specifications

Identity

Part Number
028TSMC_LVDS_01
Vendor
NTLab

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
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Frequently asked questions about Single-Protocol PHY IP

What is 1.25 Gbps LVDS IPs library?

1.25 Gbps LVDS IPs library is a Single-Protocol PHY IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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