VESA introduced the first Display Stream Compression (DSC) standard in 2014.
- VESA DSC
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
Display Stream Compression (DSC 1.2) Encoder
The Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K.
Display Stream Compression (DSC 1.2) Decoder
The Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from …
The H.265 (HEVC – High Efficiency Video Coding) Decoder IP core delivers high-performance video decompression for next-generation…
Single-core video encoder - AV1, HEVC, AVC
WAVE541C is a dual-CORE codec IP, optimally architected for real-time encoding or decoding video at 8K60 in HEVC/H.265 and AVC/H.…
Multi-format video decoder IP Core
The VC9000D enables 8K decoding with a small silicon single-core solution, or multi-core solution up to 8K@120fps, supporting AV1…
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
Multi-format, multi-stream real-time hardware decoder IP core
D300 Series is the ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers lo…
H.265 Codec - Efficiently compresses high-quality video for streaming and storage
H.265 (HEVC) is a cutting-edge video compression standard that delivers superior video quality at lower bit rates compared to H.2…
HDMI 2.1 RX PHY 12Gbps in TSMC (16nm, 12nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 Rx PHY 12Gbps in Samsung (14nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 eARC TX PHY in TSMC (16nm, 12nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 eARC Tx PHY in Samsung (14nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 eARC RX PHY in TSMC (16nm, 12nm, N6)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 eARC Rx PHY in GF (12nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 Audio PLL in TSMC (16nm, 12nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
HDMI 2.1 Audio PLL in Samsung (14nm)
The Synopsys HDMI 2.1 RX Controller and PHY IP solutions, compliant with the High-Definition Multimedia Interface (HDMI) 2.1 spec…
Single-core video decoder - HEVC, AVC, AVS2
IP