Reed Solomon Encoder IP Core

This high performance, fully configurable Reed Solomon Encoder IP Core is intended for use in a wide range of applications requiring forward error correction and can be targeted in any ASIC or FPGA technologies. In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used for channel noise elimination. The error correction capability of a FEC system is strongly depended on the amount of redundancy as well as on the coding algorithm itself. The Reed-Solomon encoder accepts a K symbol information block and outputs the information block unaltered appended with 2T parity symbols, thus forming an N symbol codeword, where N=K+2T.

ARCHITECTURE

The encoder is parameterized in terms of bits per symbol (M), maximum codeword length (N) and maximum correction power (T). It also supports shortened codes by varying on the fly the NVAL and TVAL inputs. Therefore any desirable code-rate can be easily achieved rendering the encoder ideal for adaptive FEC applications. If NVAL=2M-1 then the code is non shortened. If NVAL is less than 2M-1 then the code is shortened. The effective code rate is NVAL / (NVAL-2TVAL). The implementation is very low latency, high speed with a simple interface for applications.

• Supports many different Reed-Solomon coding  standards
• Code rate can be dynamically varied
•  Parameterizable bits per symbol (M)
• Programmable codeword length (NVAL) with  parameterizable maximum value (N)
•  Programmable number of errors (TVAL)  with parameterizable maximum value (T)
•  Shortened codes supported (NVAL,TVAL)
•  User configured primitive field polynomial
•  User configured generator polynomial
•  Synchronous design
•  Low latency  2 cycles

• Flexible
• Compact
• Cost-effective

• Verilog Source Code
• Test Bench
• Sample Syntheis scripts
• Dcumentation