SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus

The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex). The DB-SPI-M contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Slave devices.

The DB-SPI-M contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.

The DB-SPI-M targets ASIC / ASSP / FPGA integrated circuits, where typically, the microprocessor is an ARM processor, but can be any embedded processor. Figure 1 depicts the system view of the DB-SPI-M Controller IP Core embedded within an integrated circuit device.

The DB-SPI-M offers a Microprocessor a SPI Master only function in a smaller VLSI footprint than the DB-SPI-MS Master/Slave version.

• Master SPI Modes
• Half Duplex / Full Duplex Transfers – Simultaneous Transmit & Receive
• Four Signal Interface:
  • MO - Master Output (Data)
  • MI - Master Input (Data)
  • SCK - Serial Clock
  • SS[N:0] - Slave Select
• Up to N=8 Slave Select (SS) Outputs for multiple Slaves on SPI Bus
• Configurable SPI Modes:
  • Standard SPI Mode (1 Data Lane)
  • Dual SPI Mode (2 Data lanes)
  • Quad SPI Mode (4 Data Lanes)
• Programmable SPI Frame Formats:
  • Programmable SPI Frame
  • Programmable inter-frame gap
  • Programmable LSB-first or MSB-first frames
• Configurable FIFO depth for off-loading the SPI transfers from the processor:
  • Separate Transmit / Receive FIFOs
• Three Clock Domain Configuration options
• SCK Clock Generator:
  • Programmable SCK Rate
  • Programmable Clock Phase & Polarity
• Optional DMA Controller for transfers between System Memory & SPI Bus
• Internal interrupts with masking control
• Available AMBA Microprocessor Interfaces:
  • AXI / AHB / APB Buses
  • 8 / 16 / 32 bit Data Interface
• Compliance with ARM AMBA and Freescale / Motorola SPI specifications:
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASICdesign flows.

• The DB-SPI-M-AHB Controller IP Core targets embedded processor applications with high performance algorithm requirements. While most SPI controllers require high processor interaction involvement, the DB-SPI-M-AHB contains a parameterized FIFO and Finite State Machine Control for the processor to off-load the SPI transfer to the DB-SPI-M-AHB Controller. Thus, while the DB-SPI-MS-AHB is busy, independently controlling the SPI Transmit or Receive transaction of data, the processor can go off and complete other tasks.
• The DB-SPI-M offers a Microprocessor a SPI Master only function in a smaller VLSI footprint than the DB-SPI-MS Master/Slave version.

• Verilog or VHDL RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.