Learn more about Analog IP core
Analog migration projects live or die on numerous metrics – it is not easy, to say the least. Three very critical metrics are PPA, Performance, Power and Area. Here’s what most analog designers already know: when you’re porting IP to a new process, the real goal isn’t improvement—it’s preservation.
In this work, the authors introduce a general and scalable method to robustly adapt LLMs for execution on noisy, low-precision analog hardware.
Analog/mixed-signal circuits are key for interfacing electronics with the physical world. Their design, however, remains a largely handcrafted process, resulting in long and error-prone design cycles. While the recent rise of AI-based reinforcement learning and generative AI has created new techniques to automate this task, the need for many time-consuming simulations is a critical bottleneck hindering the overall efficiency. Furthermore, the lack of explainability of the resulting design solutions hampers widespread adoption of the tools.
If your device processes valuable data, controls a critical function, or connects to a wider network, it’s a target. Attackers don’t just try to break software; they increasingly physically tamper with hardware; probing, fault injecting, or opening enclosures to bypass protections and extract secrets. The consequences range from IP theft and fraud to orchestrated downtime across fleets of connected devices.
Agile Analog’s tamper detection IP is a comprehensive set of sensors and monitors designed to detect a wide variety of physical attacks and side-channel attacks (SCAs). T
When we talk about analog IC migration challenges, the conversation usually centers on device modelling, parasitic extraction, or layout density rules. But there’s an equally important aspect that can turn a successful design into a reliability nightmare: electromigration violations.
