Vendor: Cadence Design Systems, Inc. Category: CAN / CAN-FD / CAN-XL

Simulation VIP for CAN

Cadence provides a mature and comprehensive Verification IP (VIP) for the CAN (Controller Area Network) Protocol.

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Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the CAN (Controller Area Network) Protocol. The Cadence® Verification IP for CAN provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CAN helps you reduce time to test, accelerate verification closure and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

CAN is a serial communications protocol with multi-master bus access, time synchronization, and high error-detection capability. Its domain of application ranges from high-speed networks to low-cost multiplex wiring.

Supported specifications: CAN protocol versions 2.0 and 1.0, Flexible Data-Rate version 1.0, CAN XL protocol CiA 610-1 version 0.0.4.

Key features

  • CAN FD
    • Supports Flexible Data Rate
  • CAN Formats
    • Supports STANDARD and EXTENDED CAN format
  • CAN Frames
    • Supports data, remote, error and overload frames
  • CAN XL
    • Supports XL extension of the protocol which fills the gap between CAN FD and Ethernet
    • Transceiver model is required as it is not part of the VIP model.
  • Configurable Agents
    • Supports multiple CAN agent instantiations
  • Error Frames
    • Supports generation of frames with errors in particular fields, such as CRC, delimiters, and EOF
  • Fault Confinement
    • Tracks error counters and fault states
  • ISO Conformance Test
    • Supports ISO 16485 conformance test regression suite
    • Support for Section 9 of ISO conformance test suite
  • Response for DATA Frames
    • Supports generation of DATA frames in response to a REMOTE frame with a particular ID

Block Diagram

Simulation VIP for CAN block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
Simulation VIP for CAN
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.
Contact Cadence Design Systems, Inc.

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Frequently asked questions about CAN / CAN FD / CAN XL IP cores

What is Simulation VIP for CAN?

Simulation VIP for CAN is a CAN / CAN-FD / CAN-XL IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this CAN / CAN-FD / CAN-XL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CAN / CAN-FD / CAN-XL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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