Vendor: SmartDV Technologies Category: GPIO

SGPIO Verification IP

SGPIO (Serial GPIO) Bus Verification IP provides an smart way to verify the SGPIO bus.

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Verification IP View all specifications

Overview

SGPIO (Serial GPIO) Bus Verification IP provides an smart way to verify the SGPIO bus. The SmartDV's SGPIO Verification IP is fully compliant with SFF-8485 Specification Revision 0.7 Specification and provides the following features.

SGPIO Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SGPIO Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
  • Full SGPIO Initiator and SGPIO Target functionality.
  • Supports upto 256 hard disk.
  • Supports operating frequency from 33 Hz to 100 KHz.
  • Support to control SCLK High and Low time.
  • SGPIO initiator includes two blink generators A and B that may be used to control the output patterns.
  • SGPIO initiator operates in one of two modes:
    • Normal
    • General-Purpose
  • Supports below different types of registers,
    • Configuration registers
    • Receive registers
    • General purpose receive registers
    • Transmit registers
    • General purpose transmit registers
  • Callbacks in initiator, target and monitor for various events.
  • Status counters for various events in bus.
  • Notifies the testbench of significant events such as transactions, warnings,timing and protocol violations.
  • Functional coverage of complete SGPIO SFF-8485 specs.
  • SGPIO Verification IP comes with complete testsuite to test every feature of SGPIO specification.

Block Diagram

SGPIO VIP block diagram

Benefits

  • Faster testbench development and more complete verification of SGPIO designs.
  • Easy to use command interface simplifies testbench control and configuration of Initiator and Target.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the SGPIO testcases.
  • Examples showing how to connect various components, and usage of Initiator, Target and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
SGPIO VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about GPIO IP cores

What is SGPIO Verification IP?

SGPIO Verification IP is a GPIO IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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