Serial NOR Flash Memory Model
Serial NOR Flash Memory Model provides an smart way to verify the Serial NOR Flash component of a SOC or a ASIC.
Overview
Serial NOR Flash Memory Model provides an smart way to verify the Serial NOR Flash component of a SOC or a ASIC. The SmartDV's Serial NOR Flash memory model is fully compliant with standard Serial NOR Flash Specification and provides the following features. Better than Denali Memory Models.
Serial NOR Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Serial NOR Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports Serial NOR Flash memory devices like MT25QL128ABA, MT25QL512ABA, MX25L12835F, MX25L25635F, N25Q032A from all leading vendors like Macronix, Micron, Winbond and many more.
- Supports 100% of Serial NOR Flash protocol.
- Supports all the Serial NOR Flash commands as per the specs.
- Supports Single and Double Transfer Rate (STR/DTR).
- Supports following protocols in both STR and DTR
- Extended I/O Protocol
- Dual I/O Protocol
- Quad I/O Protocol
- Supports Execute-in-place (XIP).
- Supports volatile and nonvolatile configuration settings.
- Supports software reset.
- Supports 3-byte and 4-byte addressing modes.
- Supports 64-byte OTP area outside main memory.
- Readable and user-lockable
- Permanent lock with PROGRAM OTP commands
- Supports PROGRAM/ERASE SUSPEND operation.
- Supports the following ERASE capability
- Die erase
- Sector erase 64KB uniform granularity
- Subsectors erase 4KB, 32KB granularity
- Supports security and write protection
- Nonvolatile configuration locking
- Password protection
- Hardware write protection
- CRC detects accidental changes in raw data
- Supports all types of timing and protocol violation detection.
- Constantly monitors Serial NOR Flash behavior during simulation.
- Protocol checker fully compliant with Serial NOR Flash Specification.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
Block Diagram
Benefits
- Faster testbench development and more complete verification of Serial NOR Flash designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the Serial NOR Flash testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about SerDes Test / Debug IP cores
What is Serial NOR Flash Memory Model?
Serial NOR Flash Memory Model is a Test / Debug IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Test / Debug?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.