Searchable Synchronous FIFO
The FIFO-CAM controls are designed to operate over a wide range of clock frequencies.
Overview
The FIFO-CAM controls are designed to operate over a wide range of clock frequencies. The interface signals are fully synchronous; no asynchronous signals are present on either side. Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.
The contents of the FIFO buffer may be searched by a applying a search term to the ST input. If a match is found a bit-map of those locations that match are output on the EQ lines. This interface is asynchronous there being no registers within this datapath.
Key features
- Fully Synthesizable RTL - Verilog
- Static Timing Analysis compatible
- Multiple Register for synchronous pipeline
- Configurable width
- Configurable overrun depth
- Standard FIFO handshake interface
Block Diagram
Applications
- MMU Translation Buffer
- Tag buffer for tag based interfaces
- Credit buffer for credit based interfaces
- Small CAM
- Victim Cache
- Write Combining Buffer
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about FIFO / CAM IP cores
What is Searchable Synchronous FIFO?
Searchable Synchronous FIFO is a FIFO / CAM IP core from Advanced Architectures listed on Semi IP Hub.
How should engineers evaluate this FIFO / CAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FIFO / CAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.