Vendor: Thesys-Intechna Category: Comparator

RF Comparator

The TI-RF-CMP is a low power RF comparator with 4 ns propagation delay designed for using in applications, where continuous-into-…

Contact Provider Request Datasheet

Overview

The TI-RF-CMP is a low power RF comparator with 4 ns propagation delay designed for using in applications, where continuous-into-discrete signal conversion or comparison of voltages is required. The comparator can be used in digital systems for clock recovery. The device is equipped with the latching (fixation) function of the output signal. The input stage cascade is implemented in CMOS transistors providing low input bias current. The comparator operation is specified over the industrial temperature range (-40°C to +85°C).
GDSII database contains a ring of pads with built-in ESD-protection up to 2000 V.

Key features

  • Single-supply operation: 3 V to 5 V
  • 4 ns propagation delay at 5 V supply voltage
  • Up to 150 MHz input

Block Diagram

TI-RF-CMP block diagram

Benefits

  • Low input bias current
  • Latch function
  • ESD-protection

Applications

  • High-speed ADC’s
  • Digital communications
  • Clock recovery and clock distribution
  • Phase detectors
  • High speed sampling
  • Zero-crossing detector

What’s Included?

  • Datasheet
  • GDSII database
  • Customer support

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
TI-RF-CMP
Vendor
Thesys-Intechna
Type
Silicon IP

Provider

Thesys-Intechna
HQ: Russia
«Thesys-Intechna» was founded in 1993 by a Russian company «Thesys» conjunctly with a German firm «Thesys Gesellschaft für Mikroelektronik mbH» (since 1999 – one of the semiconductor divisions of «XFAB Semiconductor Foundries GmbH») as a designated representative in Russia and for joint work in the microelectronic field. We offer our experience and expertise in designing of analog-to-digital and digital-to-analog converters, analog and digital cell libraries, memory blocks, memory block compilers, Design Kits and ASICs.
Contact Thesys-Intechna

Learn more about Comparator IP core

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Improving Battery-Powered Device Operation Time Thanks To Power Efficient Sleep Mode

Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is pivotal.

Generating High Speed CSI2 Video by an FPGA

In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.

Design & Verify Virtual Platform with reusable TLM 2.0

As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate. We are sharing the experience of our company 3D-IP Semiconductors Ltd. for the development of a generic Virtual Platform using TLM 2.0; reusable for any system model.

Metric Driven Verification of Reconfigurable Memory Controller IPs Using UVM Methodology for Improved Verification Effectiveness and Reusability

The paper presents a method for verifying a standard SDRAM controller IP, based on UVM framework using the Object Oriented verification language System Verilog. The verification technique focuses on a Metric Driven approach for reconfiguring the predictor model to suit the various functional realizations of the memory controller and also to improve the performance by effectively reducing the verification cycles for maximum functional coverage.

Frequently asked questions about Comparator IP cores

What is RF Comparator?

RF Comparator is a Comparator IP core from Thesys-Intechna listed on Semi IP Hub.

How should engineers evaluate this Comparator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Comparator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP