Vendor: Rambus, Inc. Category: PCI Express

PCIe 5.0 Multi-port Switch

The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC an…

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PCIe 5.0 View all specifications

Overview

The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC and FPGA implementations enabling the connection of one upstream port and up to 31 downstream ports.

How the PCIe 5.0 Multi-Port Switch Works

The PCIe 5.0 Switch IP transparently manages upstream-downstream data flow as well as peer-to-peer transfers between downstream ports, delivering the flexibility, scalability and configurability required for connecting multiple devices, including NVMe SSDs. It enables designers to use fewer PHYs, saving latency, power consumption and costs.

The PCIe 5.0 Multi-Port Swtich has been extensively verified using commercial and internally developed VIP and test suites. It is PCI-SIG certified since 2016 and is often used as an interoperability host platform for PCIe compliance testing.

Key features

  • PCI Express Interfaces (upstream and downstream ports)
    • 1 upstream port, up to 31 downstream ports
    • Up to x16 link width per port
    • Link rate of 2.5, 5.0, 8.0, 16, and 32 Gbps per lane (Gen1, Gen2, Gen3, Gen4, Gen5 rates)
    • Supports PCI Express Base Specification Revision 5.0, and is compliant with the PCIe 4.0 and PCIe 3.1 Specifications at 16 GT/s, 8 GT/s and 5 GT/s
    • PHY Interface for PCI Express (PIPE) 5.x compliant
    • Single Virtual Channel (VC) implementation
    • Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit) for embedded endpoints
    • Configurable Receive and Replay buffer sizes
    • Advanced Error Reporting (AER) supported on each port
    • ECRC generation and check
    • ARI supported
    • Lane reversal supported
    • Independent configuration of link width, link speed, equalization settings, and PIPE interface width per-PCIe port 
    • Switch upstream port supports multiple physical functions
    • Support for Hot Plug on every downstream port
    • Access Control Services (ACS) supported
    • Optimized Buffer Flush/Fill (OBFF) supported
  • Switching Logic
    • PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
    • L1 and wake-up events forwarding
    • Peer-to-Peer transactions support between downstream ports
    • Broadcast and Multicast supported
    • Downstream Port Containment (DPC) supported
    • Round-Robin arbitration
    • No Packet buffering (cut-through architecture) for reduced latency
    • Built-in advanced data protection including ECRC, LCRC, ECC and Parity
    • Test port available for switch logic monitoring
    • Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic

Block Diagram

PCIe 5.0 Multi-port Switch block diagram

Benefits

  • Flexibility: The solution is highly configurable and scalable. For example, the designer can choose to implement up to 32 external or embedded Endpoints, and define for each port a different clock speed, data rate and throughput in order to optimize the footprint of the design.
  • 20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 5700 customers , including several hundred of ASIC tape-outs.
  • Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL.
  • Significant Latency, Power and Performance Improvements: XpressSWITCH delivers improvements in latency (using Cut-Through mode), optimization of power consumption (using embedded Endpoints), and better performance through a non-blocking architecture (using Peer-to-Peer transfers between Endpoints).
  • Demonstrated reliability: The solution has been integrated, tested and demonstrated on PLDA’s XpressKUS FPGA board running a Xilinx® Kintex® UltraScale™ device and has achieved PCI Express (PCIe®) compliance.
  • No requirement for software development: The switch will work without additional software development through the use of the configuration wizards and reference designs provided, reducing time-to-market
  • BOM/Cost savings: PCIe Embedded Switch IP enables a minimized footprint and reduces the number of chips required on the board.
  • Shorter time-to-market: PCIe Embedded Switch IP enables the reuse of existing design, reducing design time and creating independence from the SerDes Technology.

Applications

  • HPC,
  • Cloud Computing,
  • AI,
  • Machine Learning,
  • Enterprise,
  • Networking,
  • Automotive,
  • AR/VR,
  • Test and Measurement

What’s Included?

  • Verilog RTL,
  • Supporting Documentation

Specifications

Identity

Part Number
PCIe 5.0 Multi-port Switch
Vendor
Rambus, Inc.
Type
Silicon IP

Standards & Interfaces

PCIe Version
PCIe 5.0

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Rambus, Inc.
HQ: USA
Rambus delivers industry-leading chips and silicon IP for the data center and AI infrastructure. With over three decades of advanced semiconductor experience, our products and technologies address the critical bottlenecks between memory and processing to accelerate data-intensive workloads. By enabling greater bandwidth, efficiency and security across next-generation computing platforms, we make data faster and safer.
Contact Rambus, Inc.

Learn more about PCI Express IP core

Challenges in PCI Express IP Implementation

IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.

Realizing the Performance Potential of a PCI-Express IP

This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport

Frequently asked questions about PCIe IP cores

What is PCIe 5.0 Multi-port Switch?

PCIe 5.0 Multi-port Switch is a PCI Express IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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