Vendor: Rambus, Inc. Category: PCI Express

PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect

Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementat…

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Overview

Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 1.1 Controller with AXI is compliant with the PCI Express 1.1 specifications, as well as with the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification. The IP can be configured to support endpoint, root port, and dual-mode topologies, allowing for a variety of use models, and exposes a configurable, flexible AMBA AXI interconnect interface to the user. The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including number, type, and width of AXI interfaces, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power. Users may optionally enable the built-in Legacy DMA engine based on the application requirements. Rambus PCIe 1.1 Controller with AXI is the #1 choice for designers requiring enterprise-class features, highest performance, reliability, and scalability.

Key features

  • PCIe Interface
    • Complies with the PCI Express Base 4.0 Specification,
    • Supports Endpoint and rootport configuration
    • Supports x16, x8, x4, x2, x1 at Gen4, Gen3, Gen2, Gen1 speeds
    • Implements one Virtual Channel
    • Data protection (ECC, ECRC)
    • Maximum payload size of up to 4KB
    • Configurable Receive and Transmit Buffer size
    • Supports SR-IOV, 6 BARs+ EPROM and Open interrupt interface, enabling SATA Express implementation
    • Advanced features include: Advanced Error Reporting (AER), ECRC, MSI, MSI-X, ASPM and legacy power management, Lane Reversal, Hot Plug, peer-to-peer transactions, LTR
    • PIPE 4.0 and PIE-8 compliant PHY interface 32-bit/250MHz in Gen3 mode on x1, x4, x8
    • 16-bit mode supported only on x1, x4, x8 and x16
  • Supported silicon:
    • Process node/foundry agnostic digital controller
    • Interoperable with PIPE 4.0 and PIE-8 compliant analog PHY IP
    • Altera Stratix V, Xilinx Virtex-7
  • AMBA AXI Interface
    • Compliant to the AMBA AXI Specification v1.0 (AXI3) and AMBA AXI Specification v2.0 (AXI4)
    • AXI-Lite Slave interface for IP configuration
    • AXI-Lite Master interface to configure up to 8KB of user defined registers in AXI domain
    • Multiple combination (configurable) of AXI Master, AXI Slave, AXI Stream interfaces
    • Separate clock domains for each AXI interface
    • Configurable data-path (64-bits/128-bits/256-bits)
  • Data Engine and Address translation for PCIe-to-AXI and AXI-to-PCIe transfers
    • Up to 8 DMA Engines for PCIe-to-AXI, AXI-to-PCIe, AXI-to-AXI transfers Up to 4GB (block) or infinite length transfers (packet)
    • Up to 16 outstanding requests
    • Support completion reordering
    • Advanced Scatter-Gather DMA modes
    • Reporting into Scatter Gather Descriptor
    • Caching of descriptors to optimize throughput
    • Up to 16 reconfigurable address translation tables for PCIe interface
    • Up to 8 reconfigurable address translation tables per AXI4 slave interface

Benefits

  • 20+ years of experience in design of IP cores for ASIC with specialization in high-speed interface protocols and technologies, more than 6200 customers , including several hundred of ASIC tape-outs
  • Silicon target 16 nm FinFET TSMC and 28 nm roadmap
  • Configurable user interface with clock-domain-crossing provides maximum interfacing flexibility and throughput.
  • Engineered for both ASIC/SoC and FPGA implementations. Allows seamless migration from FPGA prototyping design to ASIC/SoC production design with same RTL. Fully timing closed on leading edge FPGA from Altera and Xilinx.
  • Advanced AMBA AXI interconnect enables heterogeneous SoC interfacing. Allows AXI3 and AXI4 peripherals to coexist and communicate efficiently through the interconnect interface.
  • Fully configurable communication engine features programmable DMA and Address Translation Windows, allowing flexible and high-performance AXI-to-PCIe, PCIe-to-AXI, and AXI-to-AXI data transfers.
  • Smart ordering rules management enables hazards and deadlocks prevention while ensuring optimized traffic flow.
  • Configurable error detection and reporting enables application specific error management thus simplifying application software.
  • Support for advanced Low Power states enables lower power consumption in energy-conscious applications
  • Flexible PCIe interface configuration in endpoint and root port modes. Includes ECAM support for dynamic configuration of the entire PCIe hierarchy from the AXI domain.
  • Provided with latency optimized Linux x64 PCIe device driver allowing immediate software development. Driver source code available for custom developments.

Applications

  • HPC,
  • Cloud Computing,
  • AI,
  • Machine Learning,
  • Enterprise,
  • Networking,
  • Automotive,
  • AR/VR,
  • Test and Measurement

What’s Included?

  • Verilog RTL,
  • Supporting Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
PCIe 1.1 Controller with AXI
Vendor
Rambus, Inc.

Provider

Rambus, Inc.
HQ: USA
Rambus delivers industry-leading chips and silicon IP for the data center and AI infrastructure. With over three decades of advanced semiconductor experience, our products and technologies address the critical bottlenecks between memory and processing to accelerate data-intensive workloads. By enabling greater bandwidth, efficiency and security across next-generation computing platforms, we make data faster and safer.
Contact Rambus, Inc.

Learn more about PCI Express IP core

Challenges in PCI Express IP Implementation

IP selection, verification and integration are key aspects to the success of an IP-based design. This paper describes some of the challenges imposed by an IP based implementation of the technology and discusses about possible solutions to address them.

Realizing the Performance Potential of a PCI-Express IP

This paper describes challenges involved in realizing the maximum performance of a configurable interconnect IP (GPEX - Rambus PCI Express Digital Controller). The following sections describe how various performance metrics such as roundtrip latency and bandwidth can be used to characterize a PCI Express IP performance and its impact on the system. The ideas presented can also be applied to other high speed interconnect architectures like RapidIO and Hypertransport

Frequently asked questions about PCIe IP cores

What is PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect?

PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect is a PCI Express IP core from Rambus, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI Express?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI Express IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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