Packet Classifier
Aliathon’s Packet Classification core is targeted at replacing expensive & power hungry Network Processors (NPUs) and Content Add…
Overview
Aliathon’s Packet Classification core is targeted at replacing expensive & power hungry Network Processors (NPUs) and Content Addressable Memory (CAM) for high speed, exact match look-up in the optical network packet domain.
The solution is highly scalable to fit applications from 155M - 100G and resides in a single FPGA.
Key features
- 200MHz+ push button core performance.
- Designed from the ground up to allow future protocol and channel/key scaling.
- Fully compliant with Aliathon’s existing solutions;
- 155M, 622M, 2.5G and 10G SONET/SDH (inc. PDH) solutions.
- 2.5G, 10G, 100G OTN solutions.
- Input key support from 256K to 1M.
- Fully deterministic lookup table performance up to 80Gbps.
- Fast in-band system update for dynamic rule-set support.
- Complete multi-protocol packet classification and stream ID assignment based on configurable input keys including;
- IPv4/IPv6 addresses.
- MAC addresses.
- PBB-TE/PBT/PBB tags.
- (T)MPLS labels.
- Any combination of L2/3/4 headers.
- VC/VP identifiers.
- Highly optimized memory interfaces to low cost commodity SRAM/SDRAM.
- No Content Addressable Memory (CAM )required.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about TDM Framer IP cores
What is Packet Classifier?
Packet Classifier is a TDM Framer IP core from Aliathon Ltd listed on Semi IP Hub.
How should engineers evaluate this TDM Framer?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this TDM Framer IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.