Vendor: VLSI Plus Ltd Category: MIPI

Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output

This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 …

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Overview

This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises of existing VLSI PLus IP cores, optimized for CSI2 multiplexing, and glue logic

Key features

  • Up to 4 CSI2 camera inputs
  • Each input is up to 4 data lanes
  • Output - 4 data lanes CSI stream

Block Diagram

CSI2-MUX-A1-F block diagram

Benefits

  • Simple virtual-channel based multiplexing of CSI2 camera.

What’s Included?

  • Verilog RTL
  • SDC file

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
CSI2-MUX-A1-F
Vendor
VLSI Plus Ltd
Type
Silicon IP

Provider

VLSI Plus Ltd
HQ: Israel
VLSI Plus is a boutique engineering house, providing consulting services in all areas of VLSI design, as well as complete IP cores, to be integrated in customers’ VLSI products.
Contact VLSI Plus Ltd

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Frequently asked questions about MIPI IP cores

What is Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output?

Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output is a MIPI IP core from VLSI Plus Ltd listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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