Vendor: VISENGI Category: Video Processing

M-JPEG Encoder (100 embedded quality levels)

This IP core has been developed to be a standards compliant High Speed M-JPEG Hardware Encoder.

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Overview

This IP core has been developed to be a complete standards compliant High Speed M-JPEG Hardware Encoder. It has been implemented on several ASIC and FPGA targets.

Key features

  • Baseline DCT compression (JPEG ITU-T T.81 | ISO/IEC 10918-1 with JFIF support)
  • Industry standard AXI interfaces (AXI and AXI4-stream for row-wise inputs)
  • Plug and Play IP blocks for Xilinx Vivado and Altera Quartus Qsys
  • No need for external CPU or memory.
  • On-the-fly selectable quality level/compression ratio.
  • Selectable chroma subsampling (4:4:4, 4:2:2, 4:2:0).
  • Unlimited input image size (up to 64K x 64K as per JPEG spec.).
  • Throughput: 2 compressed pixels every 3 clock cycles (constant).

Benefits

  • Compared to other JPEG IP cores this is the fastest and most versatile solution.
  • It allows a larger versatility thanks to its in built quality selection capability, so you can change the compression ratio and chroma subsampling before every image compression just by changing one register.
  • No need for any external components (CPU, DDR, ...).
  • Tailored to your very needs: Look for your part number at the core's website in order to know the exact resource requirements and maximum frequency for your FPGA part.

What’s Included?

  • Technical support
  • Documentation and design examples
  • Altera and Xilinx IP blocks
  • Instantation Templates

Specifications

Identity

Part Number
JPEG_Encoder
Vendor
VISENGI
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

VISENGI
HQ: Spain
VISENGI is a European engineering firm founded in 2009, built around an extensive knowledge and working experience on the highest throughput IP cores for data processing. We have specialized in IP core and system design of full video pipelines for FPGA and ASIC targets, leveraging ARM SoCs to enable a simple user SW control of our high speed HW IP cores. We partner with our clients not only to adapt and design our products to their very needs, but also to accompany them through their development process to insure our products are implemented to attain their full functionality within our clients' systems.
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Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is M-JPEG Encoder (100 embedded quality levels)?

M-JPEG Encoder (100 embedded quality levels) is a Video Processing IP core from VISENGI listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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