UltraLink IP Cores

UltraLink IP cores enable high-bandwidth die-to-die connectivity in advanced packaging and chiplet architectures in modern SoC and ASIC designs.

These IP cores support high-bandwidth die-to-die connectivity for advanced packaging and scale-out chiplet communication, helping designers scale heterogeneous integration with better bandwidth density, packaging flexibility, and subsystem reuse

This catalog allows you to compare UltraLink IP cores from leading vendors based on bandwidth, latency, power efficiency, and process node compatibility.

Whether you are designing advanced chiplet platforms, AI compute packages, data center silicon, or heterogeneous integration, you can find the right UltraLink IP for your application.

 
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Compare 1 UltraLink IP Cores from 1 vendors

  • 40G UltraLink D2D PHY

    Cadence Design Systems, Inc.
    • HQ: USA

    High-performance, low-latency PHY for D2D connectivity The UltraLink™ Die-to-Die (D2D) PHY enables SoC providers to deliver more …

    • GlobalFoundries
    • 12nm
    • LP
    • Silicon Proven
    Maturity: Production
    View details Contact Download datasheet

What is UltraLink IP?

UltraLink IP is a reusable interface block that implements UltraLink-based communication inside SoCs and ASICs.

It is used to build advanced multi-die systems with lower chiplet integration risk and stronger ecosystem compatibility.

Main functions of UltraLink IP

Protocol implementation

UltraLink IP provides the state machines, framing, signaling, and control behavior needed to comply with the target standard.

System integration

It connects processors, controllers, peripherals, or external devices using a verified interface architecture.

Performance and robustness

UltraLink IP is selected based on throughput, latency, interoperability, and reliability needs in the target product.

Verification and reuse

Using interface IP helps reduce bring-up risk and shortens integration time versus building protocol logic from scratch.

Key features of UltraLink IP cores

  • Standards-compliant implementation
  • Reliable interoperability
  • Low-latency communication
  • Flexible integration options
  • Reusable subsystem building block

How to choose UltraLink IP

Selecting the right UltraLink IP depends on your application and integration requirements:

  • supported standard revision and feature set
  • throughput and latency requirements
  • power and area constraints
  • verification and compliance needs
  • integration with the system architecture

Applications of UltraLink IP cores

  • advanced chiplet platforms
  • AI compute packages
  • data center silicon
  • heterogeneous integration

Compare UltraLink IP cores from leading vendors

This catalog provides access to a wide range of UltraLink IP cores from leading semiconductor IP providers.

Use filters to compare solutions based on standards-compliant implementation, reliable interoperability, low-latency communication, and integration requirements.

Frequently asked questions about UltraLink IP cores

What is UltraLink IP?

UltraLink IP is a reusable hardware block used in SoCs and ASICs to implement this function with production-ready integration, verification support, and platform reuse.

What capabilities does UltraLink IP typically provide?

Typical capabilities include performance-optimized implementation, integration with the surrounding subsystem, configurable feature support, and reuse across multiple SoC or ASIC programs.

Where is UltraLink IP used?

UltraLink IP is commonly used in advanced chiplet platforms, ai compute packages, data center silicon, and heterogeneous integration depending on the target product and architecture.

How do I choose UltraLink IP?

You should consider supported features, performance targets, power consumption, verification maturity, system integration requirements, and process node compatibility.

Why use dedicated UltraLink IP instead of building it from scratch?

Using proven UltraLink IP reduces design risk, shortens development time, and helps teams reach production faster with better interoperability and validation coverage.

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