High Throughput and Low Latency Data Compression Engine
This IP implements a proprietary modified LZ77 algorithm and provides very high speed data compression with low latency and very …
Overview
This IP implements a proprietary modified LZ77 algorithm and provides very high speed data compression with low latency and very high compression ratio. This IP can be used stand alone in data compression or it can be used as building block in GZIP and GLIB
Key features
- Compression Ratio
- Delivers the best compression ratio
- 30-40% more compression compared to competition
- Throughput
- Throughput at 4 Bytes per clock
- 5.3 Gb/s (FPGA)
- 40 Gb/s (ASIC)
- Higher throughput at 8 bytes per clock, if needed
- Latency
- 4 cycles (FPGA)
- 2 cycles (ASIC
Benefits
- Most competitor's IP either provide high throughput at low compression ratio or high compression ratio at low throughput.
- This IP provides both high throughput and high compression ratio at the same time. It has very low memory requirement.
Applications
- Networking, Storage, Big data Analytics, In place Computing
What’s Included?
- RTL(verilog)
- Test bench & tests
- Document
Specifications
Identity
Provider
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Frequently asked questions about Data Compression IP
What is High Throughput and Low Latency Data Compression Engine?
High Throughput and Low Latency Data Compression Engine is a Data Compression IP core from Proficient Design LLC listed on Semi IP Hub.
How should engineers evaluate this Data Compression?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Data Compression IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.