AES IP core

The Standard AES core family is our mid-rate solution, aimed at applications which require a few hundred Mbps throughput, whilst offering a really efficient area footprint. This core is perfect for many applications, for example wired and wireless networking, or encrypting audio or video streams. The result is a core with a particularly high speed-to-area ratio, spanning all ASIC and FPGA technologies.

Despite its compact footprint, the Standard AES family forms a very powerful and flexible platform. It has been designed in modular form and is supplied as a series of powerful, re-usable building blocks. This way, you can build up all kinds of interesting solutions where resources can be shared or replicated according to your exact requirements. The Standard family offers full AES encryption and decryption using any combination of the three AES key sizes (128-, 192-, and 256-bits). It can be used to implement any of the common block cipher modes as well as many of the more recent complex modes (take a look at our AES modes pages for more information). The table below outlines the kind of area and performance achievable using the Standard AES core.
 

• Implements AES (Rijndael) to NIST FIPS PUB 197
• Full dynamic support for all AES key sizes (128, 192 and 256-bits)
• Multiple versions available; user can choose best balance of speed and area for application
• Separate cores available for encryption and decryption
• Roundkey expansion can be split out for additional flexibility
• All NIST SP800-38A AES operating modes easily implemented (eg. ECB, CBC, OFB, CFB, CTR)
• Simple external interface
• Highly optimised for use in ASIC targets

• Fully synthesisable RTL source code
• VHDL/Verilog testbench with test vectors
• User documentation