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Chengdu Analog Circuit Technology Inc. (Actt) Founded in 2011 is a national high-tech enterprise which is specializing in the designing, licensing, the IPs (intellectual property) of the IC (integrated circuit) products, and can provide one-stop service with its clients.
Actt has been involved in low power technology field for more than 10 years. As a result, the products structure including ultra-low power analog IP, high reliability and high performance radio frequency IP and high-speed interface IP of Actt has been gradually established.
Actt is holding exceeds 200 patents in worldwide, has developed more than 500 IPs, and successively established partnerships with more than 20 fabs on a global scale. It serves hundreds of IC design enterprises worldwide, its products are widely used in 5G, IoT, smart home, automotive electronics, smart power, wearables, medical electronics, industrial control and other fields.
Actt always takes it as its responsibility to provide partners with world-leading products and services, adheres to technology innovation as its core value, committing to becoming a trustworthy and innovative world-class IP provider.
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This article explains step by step implementation of Median Filtering Algorithm in Verilog. This filtering technique is then applied to noisy image for denoising. This article also explains simple Verilog based testbench and Matlab scripts for image pre/post processing operation for verifying the same.
This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.
Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is pivotal.
In this article, we show how fast video streams conforming to MIPI CSI2 rev2.0 over MIPI DPHY rev1.2 can be generated, using VLSI Plus’ SVTPlus-CSI2-F IP core, with simple off-FPGA analog front-end. The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure.
As the system, software & IP complexity is increasing so is the demand of SystemC models & Virtual Platform for verification. To achieve it, the key requirements are that the models/platform should be developed fast, reusable & highly accurate. We are sharing the experience of our company 3D-IP Semiconductors Ltd. for the development of a generic Virtual Platform using TLM 2.0; reusable for any system model.
The paper presents a method for verifying a standard SDRAM controller IP, based on UVM framework using the Object Oriented verification language System Verilog. The verification technique focuses on a Metric Driven approach for reconfiguring the predictor model to suit the various functional realizations of the memory controller and also to improve the performance by effectively reducing the verification cycles for maximum functional coverage.