Learn more about SRAM IP core
This Position Paper describes a family of Power Management IP solutions integrated by Dolphin Integration’s customers into their SoC to drastically improve Energy Efficiency (EE). SoC performance metric is changing, moving from pure performance metric (GHz or MIPS) to performance efficiency and minimum power consumption. This new metric, already crucial for IoT or mobile devices, is becoming key in various applications, like automotive, embedded or space.
Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC (System on Chip). For such applications, the design of the “Always-On power domain" (a.k.a AON power domain) is pivotal.
The memory hierarchy (including caches and main memory) can consume as much as 50% of an embedded system power. This power is very application dependent, and tuning caches for a given application is a good way to reduce power consumption. However application programs are complex and include many subroutines, each of them having their own optimal cache configuration. We developed a low power dynamically reconfigurable cache controller and its simulator called Cache Evaluation Software.
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vincent van der Leest, Synopsys
