Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
SRAM
Silterra 0.18um ULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via ROM Compiler
VeriSilicon SMSB 0.18um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor …
Overview
VeriSilicon SMSB 0.18um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor Manufacturing Corporation (SMSB) 0.18um 1P6M Ultra Low Leakage 1.8V/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.
Key features
- Low Leakage
- Low Power
- High Density
- High Speed
- Automatic Power Down
- Tri-State Output(SRAM only)
- Write Mask Function(SRAM & Register File)
- More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Silterra | 180nm | G | Pre-Silicon |
Specifications
Identity
Part Number
SMSB18ULL
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Provider
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
HQ:
USA
VeriSilicon Microelectronics (Shanghai) Co., Ltd. (VeriSilicon, 688521.SH) is committed to providing customers with platform-based, all-round, one-stop custom silicon services and semiconductor IP licensing services leveraging its in-house semiconductor IP. Under the unique "Silicon Platform as a Service" (SiPaaS) business model, depending on the comprehensive IP portfolio, VeriSilicon can create silicon products from definition to test and package in a short period of time, and provides high performance and cost-efficient semiconductor alternative products for fabless, IDM, system vendors (OEM/ODM), large internet companies and cloud service provider, etc. VeriSilicon's business covers consumer electronics, automotive electronics, computer and peripheral, industry, data processing, Internet of Things (IoT) and other applications.
VeriSilicon presents a variety of customized silicon solutions, including high-definition video, high-definition audio and voice, in-vehicle infotainment, video surveillance, IoT connectivity, smart wearable, high-end application processor, video transcoding acceleration and intelligent pixel processing, etc. In addition, VeriSilicon has six types of in-house processor IPs, namely GPU IP, NPU IP, VPU IP, DSP IP, ISP IP and Display Processor IP, as well as more than 1,400 analog and mixed signal IPs and RF IPs.
Founded in 2001 and headquartered in Shanghai, China, VeriSilicon has 7 design and R&D centers in China and the United States, as well as 11 sales and customer service offices worldwide. VeriSilicon currently has more than 1,200 employees.
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Frequently asked questions about SRAM IP cores
What is Silterra 0.18um ULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via ROM Compiler?
Silterra 0.18um ULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for silterra Pre-Silicon.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.