Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
VeriSilicon SMIC 0.11um Ultra Low-Leakage Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Cor…
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 130nm | G | Pre-Silicon |
SMIC 0.13um 90% shrunk HVT Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Pre-Silicon.
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