Quad-SPI FLASH Controller AHB

Overview

The Veriest Serial Flash Controller Design IP offers a rich set of features to facilitate easy access to Serial Flash devices. The CPU can boot directly from the Serial Flash through the memory emulation interface. Alternatively the Serial Flash controller can copy a code image from the serial Flash device to CPU instruction memory prior to CPU boot. The Serial Flash Controller has an internal DMA controller which can be configured to copy code from the serial flash device to any target destination in the system. The Serial Flash Controller is compatible with advanced Flash devices supporting Quad-SPI and Execute-in-Place (XIP) as well as legacy devices using serial SPI. There are also useful features such as Device Detection, Serial Flash Integrity check using CRC-32 Serial FLASH image write and Device Direct Access to gain access to all the internal register set of the serial flash device.

Key Features

AHB Memory Mapped Access
Auto-Copy DMA Boot Support
DMA controller
Flash Device Direct Access
Serial Flash Device Detect
Built-In-Self-Test (BIST)
SPI Serial Mode
SPI Quad Mode
Bit Banging
3 / 4 Byte Addressing
XIP Execute-In-Place
AHB Slave Interface
AHB Master Interface
APB Slave Interface
Boot Control Interface
Interrupt
Configuration and Status Registers
SFLASH Image Write
SPI clock rate configurable

Benefits

Low Gate Count
Low Power Consumption
Fully Verified in with Advanced Function Verification
Spyglass Lint Validated
Standards Compliant
Silicon Proven Core

Block Diagram

Applications

General System on Chip Use

Deliverables

Synthesizable Verilog RTL
Verilog test bench and test cases
System Verilog verification environment and test cases
Detailed block diagram and technical documents

Technical Specifications

Maturity

Silicon proven

Availability

Now

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