The MVD MPEG TS Serializer core is a drop-in module that includes the following functions:
• Incoming MPEG_TS clock resynchronization
• x47 sync signal recovery
• Parallel/Serial Conversion
• Auto adaptation to 188/204/208 bytes packet Input
• 188 bytes MPEG-TS serial output
• No coding mechanism
MPEG TS Serializer
Overview
Key Features
- Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
- Full synthesizable RTL VHDL design (not delivered) for easy customization
Block Diagram
Applications
- MVD MPEG TS Serializer may be used in applications related to DVB/MPEG-TS transport streams for Serial Data transmission between FPGA.
Deliverables
- Datasheet
- Netlist for core generation
- VHDL top file
- VHDL source code : can be delivered as an option under NDA and other specific clauses
Technical Specifications
Availability
Available
Related IPs
- Rx MPEG TS Interface
- MPEG TS Deserializer
- ETR101290 IP core (Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06))
- 1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- 32:1 serializer followed by sub-LVDS drivers
- Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain