Low-Noise Bandgap Reference - Low Noise: 63nV/?Hz, PSRR: -80dB TSMC 0.18um CMOS (CLM18)

Overview

This macro-cell is a low noise, high PSRR voltage reference core designed for TSMC 0.18um (CLM18) CMOS technology. The core is ideal for applications where noise performance is critical. The circuit generates a buffered 1.185V, temperature-compensated bandgap voltage reference (40ppm/oC). A 5-bit trimming is available and guarantees ±1.5% output voltage accuracy. A 25uA reference current source (PTAT) for external use is also included.

Key Features

Reference Voltage: 1.185V ±1% (w/ trimming)
Low noise: 63nV/?Hz (10Hz to 25kHz)
High PSRR: –80dB (up to 100kHz)
Temperature compensated: < 40ppm/oC
Supply voltage: 5.0V ±10%
Buffered reference output: 100uA (max)
PTAT reference current output available
Area: 0.101mm2

Block Diagram

Applications

Battery powered equipment
Active RFID tag ICs
Energy Haversting ICs
Hearing Aids

Deliverables

Datasheet/Integration Guide
HDL Model
Flat GDSII database/LVS netlist
Customer Support

Technical Specifications

Foundry, Node

TSMC 0.18um CMOS (CLM18)

Maturity

Silicon Available

TSMC

Pre-Silicon: 180nm G

Request Info