The SuperRAM implements a hardware accelerator for zram compression and decompression. SuperRAM implements a ZeroPoint proprietary compression algorithm and is optimized for power efficiency, high throughput and high compression efficiency.
SuperRAM is integrated on the SoC as other hardware accelerators, as a master node on the SoC interconnect. Part of the integration includes a software driver so that the zram crypto-compress API sends a command to the SuperRAM accelerator when there is a software-triggered compression and decompression.
High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
Overview
Key Features
- Compression ratio: 2-4x across diverse data sets
- Compression throughput: 8GB/s
- Decompression throughput: 10.5GB/s
- Frequency: DDR4/DDR5 DRAM speed
- IP area: Starting at 0.1mm2 (@5nm TSMC)
- Memory technologies supported: (LP)DDR4, (LP)DDR5, HBM
- SuperRAM IP is compatible with all DRAM technologies and supports standard interfaces such as AXI and CHI. Other proprietary interfaces can be supported upon request.
Benefits
- High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
- Off-loading CPU – More cycles to released to user work loads
- Power efficiency – Less energy
- Speed – Fast compression and low latency access
- Several in-flight compression and decompression operation operating in parallel
- Operating at main memory speed and throughput
- Compatible to AXI4/CHI, both 128-b and 256-b bus interface
- Intelligent real-time analysis and tuning of the IP Block
Applications
- Smart device SoCs and Server CPUs.
- Smart device SoCs: The product benefit is a better user experience at unmatched power efficiency when the host processor is offloaded and the page swapping is hardware accelerated.
- Server CPUs: The product benefit is more system performance at less power when SW-based compression is off-loaded from the the host. Operating system and hypervisor offload SW-based compression of swapped pages with a super-fast page compression technology and return more performance to the guest at unmatched power efficiency.
Deliverables
- Synthesizable Verilog RTL (encrypted)
- Implementation constraints
- UVM testbench (self-checking)
- Vectors for testbench and expected results
- User Documentation
Technical Specifications
Foundry, Node
TSMC 7nm, 5nm, 3nm
Maturity
Tape-out
Availability
Immediate
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