Configurable AES Core
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies.
Overview
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a flexible trade-off of key size, modes and throughput with area to get the most optimized solution. The base suite consists of Encryption, Decryption, Key Expansion and Cryptographic Mode modules that together cover all the combinations required for encryption and authentication. All modules support the three key sizes, dynamically selectable per-packet.
For the lowest gatecount the modules can be configured to support only one key size. In addition all modules are available with AMBA AXI, AHB, APB interfaces.
Key features
- Simple register based interface
- Run-time support for 128, 192 and 256 bit keys
- 14, 16 and 18 clock cycle cipher/decipher for 128-bit/192-bit/256-bit keys respectively
- 130x faster than a software only implementation
- Integrated key expansion
- Cipher-Block-Chaining (CBC) / CBC-MAC support
- Counter chaining (CTR) support
- Galois Counter Mode (GCM)
- Galois Message Authentication Code (GMAC) support
- Support for CCM/CCM* through software sequencing of CBC-MAC and CTR
- Option of AMBA 3 APB or AHB, AXI interfaces
What’s Included?
- RTL source code
- Testbench
- Synthesis and STA scripts
- Comprehensive documentation
Specifications
Identity
Provider
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Frequently asked questions about Symmetric Cryptography IP cores
What is Configurable AES Core?
Configurable AES Core is a Symmetric Crypto IP core from EnSilica listed on Semi IP Hub.
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.