CCSDS 131.2 SCCC Turbo Encoder and 64-APSK Modulator
The IPrium-CCSDS-SCCC-Modulator-Encoder IP Core implements the CCSDS modulation standard 131.2-B.
Overview
The IPrium-CCSDS-SCCC-Modulator-Encoder IP Core implements the CCSDS modulation standard 131.2-B. The IP Core is a complete digital QPSK, 8-PSK, 16-APSK, 32-APSK and 64-APSK modulator with an integrated Serially Concatenated Convolutional turbo encoder (Turbo SCCC), optimized for high-capacity satellite systems.
Key features
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
- Fully verified and real-time tested on a FPGA based development platform
- Considerations for easy ASIC integration
- Validated on IPrium Evaluation Boards
What’s Included?
- VQM/NGC/EDIF netlists for Intel (Altera) Quartus Prime, Xilinx Vivado/ISE, Lattice Diamond or Microsemi (Actel) Libero SoC
- IP Core testbench scripts
- Design examples for Intel (Altera), Xilinx, Lattice, and Microsemi (Actel) evaluation boards
- Free 1 year warranty and support period
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about Modulation and Demodulation IP cores
What is CCSDS 131.2 SCCC Turbo Encoder and 64-APSK Modulator?
CCSDS 131.2 SCCC Turbo Encoder and 64-APSK Modulator is a Modulation Demodulation IP core from IPrium LLC listed on Semi IP Hub.
How should engineers evaluate this Modulation Demodulation?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Modulation Demodulation IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.