Vendor: Noesis Technologies Category: Modulation Demodulation

Configurable Soft Output Demapper

Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system.

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Overview

Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system. The receiver extracts the phase and magnitude of the carrier signal. Subsequently a decision must be taken on the actual transmitted bits. Due to channel noisy conditions, the received signal has been distorted and there are positional errors on the constellation points. The ntSOD Soft Output Demapper IP Core implements the LLR (Log Likelihood Ratio) algorithm to convert the received distorted modulated signal from its complex I, Q form to a bit stream. It identifies the actual transmitted symbol bits and assigns to each bit a level of confidence in the format of a soft value. It sup-ports various modulation levels such as BPSK, QPSK, 16 QAM and 64 QAM. This soft-bit information can be subsequently used during ECC decoding process by a soft-input ECC decoder such as Viterbi Decoder. Soft decision ECC decoding can provide a coding gain of 2 dB for 3 soft-bits per encoded bit or 2.2 dB for 4 soft bits per encoded bit when compared with hard decision ECC decoding. The soft-bit infor-mation can be configured in sign-magnitude or 2’s complement format.

Key features

  • Soft output demapper based on the LLR (Log Likelihood Ratio)algorithm.
  • Parameterized number of soft bits per symbol .
  • Parameterized architecture depending on supported modulation levels for optimum resources utilization.
  • Programmable modulation level.
  • Supports BPSK, QPSK, 16 QAM, 64 QAM constellations.
  • Supports 2’s complement of sign-magnitude soft output arithme-tic format.
  • Compact design that requires approximately 500 Virtex-2 CLB slices.
  • Fully synchronous design, using single clock.
  • Silicon proven in Xilinx FPGA technologies for a variety of appli-cations.

Block Diagram

ntSOD block diagram

What’s Included?

  • Fully commented synthesizable VHDL or Verilog source code or
  • FPGA netlist.
  • VHDL or Verilog test benches and example configura-tion files.
  • Comprehensive technical documentation.
  • Technical support.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
ntSOD
Vendor
Noesis Technologies

Provider

Noesis Technologies
HQ: Greece
Noesis Technologies specializes in design,development and marketing of high quality, cost effective communication IP cores and provides expert ASIC/FPGA design services in telecom DSP area. Our solutions are key components to the most sophisticated telecom systems. Backed-up by our leading-edge expertise on forward error correction, encryption and networking technology as well as on DSP algorithm development we provide robust solutions that are used to improve data quality, increase bandwidth or reduce the overall system cost of end-application.
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Frequently asked questions about Modulation and Demodulation IP cores

What is Configurable Soft Output Demapper?

Configurable Soft Output Demapper is a Modulation Demodulation IP core from Noesis Technologies listed on Semi IP Hub.

How should engineers evaluate this Modulation Demodulation?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Modulation Demodulation IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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