Vendor: SmartDV Technologies Category: GPIO

BISS Verification IP

BISS Verification IP provides an smart way to verify the BISS component of a SOC or a ASIC.

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Verification IP View all specifications

Overview

BISS Verification IP provides an smart way to verify the BISS component of a SOC or a ASIC. The SmartDV's BISS Verification IP is fully compliant with standard BISS Specification and provides the following features.

BISS Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

BISS Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Fully compatible with Standard BISS Specification.
  • Transmit and receive commands allow the user to transmit and receive BISS data.
  • Configurable Baud rate control.
  • Fully configurable serial interface.
  • Configurable receive FIFO depth.
  • Supports constraints Randomization.
  • Callbacks in Master, Device and monitor for user processing of data.
  • Supports for standardized data format.
  • Supports BISS standard rotary encoder.
  • Supports point-to-point and bus configuration.
  • Supports broadcast and addressed command frame.
  • Supports MA clock frequency from 80 KHZ.
  • Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
  • BISS Verification IP comes with complete test suite to verify each and every feature of BISS specification.
  • Status counters for various events in bus.
  • Functional coverage for complete features.

Block Diagram

BISS VIP block diagram

Benefits

  • Faster testbench development and more complete verification of BISS designs.
  • Easy to use command interface simplifies testbench control and configuration of Master and Device.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the BISS testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
BISS VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

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Frequently asked questions about GPIO IP cores

What is BISS Verification IP?

BISS Verification IP is a GPIO IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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