SPI XIP Flash Memory Controller IP – Programmable IO & Execute-In-Place (XIP) via second AMBA Interface

The DB-SPI-XIP-FLASH-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad/Octal SPI Flash Memory devices by way of Processor Execute-in-Place (XIP).

The DB-SPI-XIP-FLASH-AMBA is a SPI Master Controller targeting SPI NOR/NAND Flash Memories. The DB-SPI-XIP-FLASH-AMBA contains two AMBA Slave Interfaces: the first for Processor configuration or Processor access to the Flash Memory; the second for Processor AMBA Interface for Execute-in-Place (XIP) access to Flash Memory.

Figure 1 depicts the system view of the DB-SPI-XIP-FLASH-AMBA Controller IP Core embedded within an integrated circuit device, with many optional Slave AMBA interface options. The DB-SPI-XIP-FLASH-AMBA contains an AXI or AHB Slave allowing for XIP Memory Read of Flash Memory via the SPI Master Bus, and AXI/AXI-Lite, AHB, or APB Slave Interface for Processor Configuration or Memory Read/Write of Flash Memory.

• Master SPI Controller with two AMBA interfaces to access SPI Flash Memory:
  • AXI/AHB/APB Slave Interface for CPU Configuration & direct read/write of SPI Flash Memory.
  • AXI/AHB Slave Interface for Execute-In-Place (XIP) – accepts AXI/AHB Slave read requests, reads the SPI Flash Memory, and returns the read data
• SPI Flash Memory Support & Interface:
  • Supports Execute-In-Place (XIP), CPU Programmable IO, and DMA. Customers can order with CPU Programmable IO and add any of theadditional features as required.
  • Flash Memory from Adesto, Cypress/Spansion, Macronix, Micron, and Winbond
  • Supports SPI Mode0, Mode3 at 200 MHz
  • Up to N=8 Slave Select (SS) Outputs supporting multiple SPI Flash Memory devices. N=16 optional.
  • Configurable SPI Modes:  Standard SPI Mode (1 Data Lane) Dual SPI Mode(2 Data lanes) Quad SPI Mode Octal Mode(4 Data Lanes)(8 Data lanes)
  • Single and Double Transfer Rate (STR/DTR)
  • Programmable SPI Command, Address, Dummy Cycle (latency), and Data lengths
  • Programmable LSB-first or MSB-first Per Word
• Transmit/Receive FIFOs:
  • Dual-Clock designs
  • User configurable depths
• Two Clock Domains:
  • AMBA Bus / SCK Clocks
• Internal interrupts with masking control
• Available AMBA Microprocessor Interfaces:
  • AXI / AHB / APB Buses
  • 8 / 16 / 32 bit Data Interface
• Compliance with ARM AXI4/ AXI3 / AHB / APB AMBA specifications:
  • Compliance with AMBA AXI Protocol Specification (V2.0)
  • Compliance with AMBA APB Protocol Specification (V3.0)
  • Compliance with AMBA Specification (V2.0) - AHB
  • Compliance with AMBA 3 AHB-Lite Protocol (V1.0)
• Compliance with ARM AMBA and Freescale / Motorola SPI specifications:
• Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, no gated clocks, and no internal tri-states, for easy integration into FPGA or ASICdesign flows.

• Verilog RTL Source or technology-specific netlist.
• Comprehensive testbench suite with expected results.
• Synthesis scripts.
• Installation & Implementation Guide.
• Technical Reference Manual.