DAC 2024 - Showcasing the future of RISC-V through EDA
Brett Cline, Codasip
Vendor:
Socionext Europe GmbH
Category:
DAC
8-bit <=120GSa/s Ultra-high-speed DAC in TSMC 16nm CMOS
DAC IP Macro.
Overview
DAC IP Macro.
Originally developed for high speed optical communication systems but used in many other applications
Low power consumption
Small area
Simple integration process
Generic, flexible, silicon-proven
Larger range of IP Macro family is available
Field proven: many different variants deployed in various devices in the market
Development Kits for initial evaluation available (SNEUADCDAC16H)
Key features
- DAC with ultra-high sampling rate, low power, high BW, high ENOB
- Process technology: 16nm
- Resolution: 8 bit
- Sampling rate: 70 – 120 GSa/s
- Differential analogue input: 800mVPPDIFF
- Output clock @Fs/128 to digital core per channel
- Bandwidth (-3dB): 0.31*Fs
- Fully programmable and high performance fractional DPLL
- Available in single channel, IQ pair, 2x IQ pair and 4x IQ pair
- Fully specified for -5C to 100C operation
- APB control interface
Block Diagram
SNEUDAC120H16 block diagram
Benefits
- Socionext has over 40 years’ experience and is a leader in state-of-the art system-on-chip technology and provides high performance SoC designs, serial transceiver technologies and advanced packaging solutions.
- Socionext combines specialist high-speed analogue, mixed-signal and digital designs having SoCs with large capacities, small sizes, and low power consumption through realization of 40nm, 28nm, 16nm and further advanced technologies.
- Therefore, in addition to IP offering , also total SoC (ASIC) solutions that include proven high-speed and large-pin-count package design, and verification can be supported/provided.
- IP and Base Technology for the most Advanced Digital Coherent SoCs including:
- Low-power, high-speed ADC
- Low-power, high-speed DAC
- Low-power High-speed VSR/MR/LR SerDes (1–56 Gb/s)
- Jitter Cleaning PLLs
- Temperature Sensor
Applications
- Wireline /Optical Networking / OTN
- Wireless / Satellite Communication
- Antenna / Phased-Array Communication Sytems/MIMO
- Test & Measurement Equipment
- Industrial and Customer applications
What’s Included?
- Documentation: Datasheet, User Guides, Test Report
- Hard Macro & integration support
- Abstract LEF and timing LIB files with constraints
- Behavioral Verilog model
- Example test bench
- Layout/Package guide
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 16nm | 16nm 160 nm | Silicon Proven |
Specifications
Identity
Part Number
SNEUDAC120H16
Vendor
Socionext Europe GmbH
Type
Silicon IP
Analog
Resolution bits
8 Bit
Provider
Socionext Europe GmbH
HQ:
Germany
Socionext is a leading global provider of System-on-Chip Solutions, headquartered in Yokohama, Japan. The company designs, develops and delivers System-on-Chip products to customers worldwide. Founded in 2015, Socionext is a new, innovative company providing industry-leading solutions. The company is focused on technologies that drive today’s leading-edge applications in consumer, automotive and industrial markets and provides dynamic technologies that drive today’s leading-edge applications.
Combining world-class technical expertise, market know-how, and many years of experience, Socionext offers a broad IP portfolio, state-of-the-art implementation expertise, and best-in-class customer support ensuring a reliable, high quality experience for customers.
Socionext Europe GmbH plays a major role in the company’s worldwide activities from our headquarters in Langen, near Frankfurt (Germany) and offices in Neuried/Munich (Germany) and Maidenhead (UK).
Learn more about DAC IP core
Making the most of the 60th DAC
Brett Cline, Codasip
DAC 2022 - Is it too risky not to adopt RISC-V?
Brett Cline, Codasip
Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
DAC: The View from Wall Street
DAC Panelists Discuss Emulation's Versatility & Various Use Models
Lauro Rizzatti, Verification Consultant
Frequently asked questions about DAC IP cores
What is 8-bit?
8-bit is a DAC IP core from Socionext Europe GmbH listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
How should engineers evaluate this DAC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.