Vendor: Eureka Technology, Inc. Category: PCI

32-bit PCI Bus Master/Target

32-bit PCI Bus Master/Target

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Key features

  • Compliant with PCI specification 2.2/2.3/3.0 protocol.
  • Designed for ASIC and FPGA implementations in various system environments.
  • Combines bus master and bus target functions in one core.
  • Supports burst transfer to maximize memory bandwidth.
  • Zero wait state PCI data transfer. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.
  • Supports target retry, disconnect and target abort.
  • Automatic transfer restart on target retry and disconnect.
  • Concurrent bus master and target function.
  • Write buffer for target write data posting to increase PCI bus performance.
  • Responds to standard PCI configuration access.
  • Supports all PCI specific configuration registers.
  • User controlled base address register sizing and mapping.
  • Retry counter to limit bus access to non-responsive target device.
  • PCI status directly available to user logic for interrupt generation.
  • Differentiating Features
    • Asynchronous user interface
    • Power management.
    • DMA controller.
    • Direct interface to AMBA AHB, Mips or Power PC.
    • Dual address cycle.
    • Hot swap for compact PCI.
    • Host bridge function.

Block Diagram

EC220 block diagram

Specifications

Identity

Part Number
EC220
Vendor
Eureka Technology, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Eureka Technology, Inc.
HQ: USA
Eureka Technology Inc. provides reusable IP cores for ASIC, PLD and system designs. These system level function cores are designed to:
  • Shorten Time-to-market
  • Eliminate Design Risks
  • Reduce Development Costs
As today's technologies evolve in a very fast pace, design engineers are constantly looking for ways to speed up the design cycle in order to have product in the market ahead of the competitions. The use of reusable IP cores in IC and system design has emerged as the methodology of choice to address the needs for rapid productization, fast prototyping and software/hardware co-development. Eureka Technology help design engineers stay in the forefront of this new design methodology by providing reusable IP cores. Our reusable IP cores are silicon proven and pre-verified to meet and exceed customer requirements. Design risk is virtually eliminated since each one of these cores has been fully tested and proven in real world applications. Since founded in 1993, Eureka Technology has established itself as a leading reusable IP core provider with customer base in the United States, Japan, and Europe. We have provided reusable IP cores to many market leaders in the computer, electronics and semiconductor industries. Our technologies have been incorporated into tens of million dollars' worth of products sold by our customers. We also have entered partnership agreements with leading silicon vendors to incorporate our reusable IP cores into their silicon products. However, our important partnership is the one with our customers and we would like to be the design partner for your next project.
Contact Eureka Technology, Inc.

Learn more about PCI IP core

PCI Express 3.0 needs reliable timing design

PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard.

Frequently asked questions about PCI IP cores

What is 32-bit PCI Bus Master/Target?

32-bit PCI Bus Master/Target is a PCI IP core from Eureka Technology, Inc. listed on Semi IP Hub.

How should engineers evaluate this PCI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PCI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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