Vendor: NTLab Category: High-Speed

3.125 Gbps DDR CML receiver

065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin E…

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TSMC 65nm GP Silicon Proven View all specifications

Overview

065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD_INN are differential input pins that should be connected to bonding pads. Buffer includes two 50-Ohm on-chip termination resistors, connected to supply voltage node. So the interface supports both AC and DC-coupled connections. IREF_RX is a reference current input.
 

Key features

  • TSMC CMOS 0.065 um
  • 1.2 V digital power supply
  • 2.5 V CMOS input logic signals
  • 1.2 V CMOS input logic signals
  • 3.125 Gbps (DDR MODE) switching rates
  • Temperature range: -40 °C to + 125 °C
  • Optimized for pad-limited layout design
  • Portable to other technologies (upon request)

Block Diagram

065TSMC_CML_01 block diagram

Applications

  • Point-to-point data transmission
  • Multidrop buses
  • Clock distribution
  • Backplane receiver
  • Backplane data transmission
  • Cable data transmission

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 65nm GP Silicon Proven

Specifications

Identity

Part Number
065TSMC_CML_01
Vendor
NTLab

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
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Learn more about High-Speed IP core

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Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.

Frequently asked questions about High-Speed I/O Pad IP

What is 3.125 Gbps DDR CML receiver?

3.125 Gbps DDR CML receiver is a High-Speed IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this High-Speed?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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