128x16 Bits OTP (One-Time Programmable) IP, X-FAB XR013 2.5V SOI Process
The AT128X16B130XR0BA is organized as 128 words by 16 bits one-time programmable in 16-bit read and 1-bit program modes.
Overview
The AT128X16B130XR0BA is organized as 128 words by 16 bits one-time
programmable in 16-bit read and 1-bit program modes. This is a type of non-volatile memory fabricated in XR013 SOI process using 2.5V I/O devices only. The OTP can be widely used in chip ID, security key, memory redundancy, parameter trimming, configuration setting, feature selection, and PROM, etc.
Key features
- Fully compatible with X-FAB 130nm CMOS technology
- Low voltage: 2.25–2.70V read voltage, 3.55V±5% program voltage
- High speed: one-bit program at a time with 10µs, 500ns read cycle time for 16bits
- Wide temperature range: from -40°C to 125°C
- Asynchronous address and control input and latched output
- Built-in fuse protection circuits
Benefits
- Small IP size
- Low program voltage/current
- Low read voltage/current
- High reliability
- Wide operating temperature
- Silicon characterized and qualified
What’s Included?
- Datasheet
- Verilog behavior model and test bench
- Timing library
- LEF File
- Phantom GDSII database
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| X-FAB | 130nm | XR013 | Available on request |
Specifications
Identity
Provider
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Frequently asked questions about eFuse / OTP IP cores
What is 128x16 Bits OTP (One-Time Programmable) IP, X-FAB XR013 2.5V SOI Process?
128x16 Bits OTP (One-Time Programmable) IP, X-FAB XR013 2.5V SOI Process is a eFuse / OTP IP core from Attopsemi Technology listed on Semi IP Hub. It is listed with support for x-fab Available on request.
How should engineers evaluate this eFuse / OTP?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this eFuse / OTP IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.