Vendor: NTLab Category: DAC

10-bit 1-channel constant power DAC

10-bit constant power DAC employs a current steering DAC architecture with control loop, which adjusts DAC input code to keep pow…

Overview

10-bit constant power DAC employs a current steering DAC architecture with control loop, which adjusts DAC input code to keep power dissipated in terminator constant. The block is easy to configure and operate, combining good accuracy and linearity. Several operation modes are available: constant power DAC, current DAC with output voltage monitoring, current DAC (manual mode), low-speed ADC. Output DAC current could be fed to one of two DAC outputs (DAC_OUT0 or DAC_OUT1) depending on Out_sel input. IP 250iHP_DAC_02 is modified version of previously designed Constant power DAC - 250iHP_DAC_01. Design modification was targeting change of output current polarity. In order to do this, following changes were made: pmos-type current mirrors 250iHP_CM_05a were added at outputs DAC_OUT0, DAC_OUT1; ADC inputs are separate pins now to probe voltage at outputs of 250iHP_CM_05a cells; ADC output is inverted to deal with changed output current and voltage polarity.

Key features

  • iHP SiGe BiCMOS 0.25 um
  • Single 2.5 V supply voltage
  • 22 mA full scale output current
  • 0°C to 100°C operation
  • 4 active operation modes
  • Standby mode

Block Diagram

Applications

  • Supply voltage stabilization systems
  • Measurement and calibration systems

What’s Included?

  • Schematic
  • Layout
  • Abstract view (.lef and .lib files)
  • Verilog behavior model
  • GDSII
  • DRC, LVS, antenna reports
  • Documentation

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
250iHP_DAC_02
Vendor
NTLab
Type
Silicon IP

Analog

Resolution bits
10 Bit

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 10-bit 1-channel constant power DAC?

10-bit 1-channel constant power DAC is a DAC IP core from NTLab listed on Semi IP Hub.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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