小芯片技术可一次性同步助力项目设计突破

By Majeed Ahmad, EDN (June 13, 2023)

What’s the state of chiplet technology today? As the cost advantages of silicon process scaling driven by Moore’s law start to dwindle, will the chiplet approach replace system-on-chip (SoC) designs with multi-die heterogeneous implementations? Are small steps toward implementing chiplet technology sufficient for this landmark semiconductor industry undertaking?

There is no simple answer to these questions yet. But one thing is clear: multi-die architectures are becoming increasingly critical in handling the needs of compute-intensive applications in data centers, cloud computing, and generative artificial intelligence (AI), technologies that require large amounts of memory and fast inter-chip communications.

Then there are automotive and gaming applications that mandate much more reliable and cost-effective solutions than what the current advanced packaging solutions can offer. So, where do the high-performance and highly scalable multi-die architectures for compute-intensive applications actually stand?

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