Cadence工具获台积电7纳米早期设计及10纳米芯片生产认证
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
Related News
- Cadence数字和定制/模拟设计流程成功通过最新TSMC N2 认证
- TSMC认证Synopsys IC Compiler II适合10-nm FinFET生产，并开始7-nm工艺的初步设计
- Synopsys的IC Compiler II通过了TSMC 7nm制程工艺认证
- Cadence获得TSMC 7nm工艺技术认证