The PCI Express® (PCIe®) Controller IP is a configurable, performance-optimized core designed for ASIC and FPGA integration.
- PCI Express
The PCI Express® (PCIe®) Controller IP is a configurable, performance-optimized core designed for ASIC and FPGA integration.
112G LR-Max Ethernet PHY for TSMC N5
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networki…
The PCI Express® (PCIe®) 6.1 Controller with AXI is configurable and scalable controller IP designed for ASIC implementation.
The PCI Express® (PCIe®) 6.1 Controller is configurable and scalable controller IP designed for ASIC implementation.
PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
PCIe 6.0 (Gen6) Premium Controller
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
The configurable and scalable Controller IP for PCI Express® (PCIe®) 6.x supports all required features of the PCI Express 6.x sp…
PCIe Gen 6 Phy
The PCIe Gen 6 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 6 interfa…
PCIe Gen 6 controller IP
Truechip's CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of a…
CXL 4.0/3.2/3/2 Verification IP
The CXL Verification IP provides an effective & efficient way to verify the components interfacing with CXL interface of an IP or…
The PCIe Switch Verification IP provides an effective & efficient way to verify the components interfacing with the PCIe Switch i…
The PCIe Gen 5 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 5 interfa…
Our latest PCIe gen 6 controller IP, which is "NoC aware", provides a high-speed interface for efficient data transfer and system…
1-56Gbps Serdes - 7nm (Multi-reference Clock)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Ultra Low Latency)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…
1-56Gbps Serdes - 7nm (Area-optimized)
The architecture utilizing DSP techniques demonstrated excellent scalability over data rates and insertion losses, superior relia…