Vendor:
T2M GmbH
Category:
USB
USB 3.0 Gen1 / Gen2 Device Controller IP
We provide configurable and scalable USB 3.0 host/device/dual mode controller IP Core for a wide range of applications.
Overview
We provide highly configurable and scalable USB 3.0 host/device/dual mode controller IP Core for a wide range of applications. The USB 3.0 controller is designed for compliance with USB3.0 specification, Revision 1.0 and all associated ECN’s, as well as USB specifications Rev 2.0 and all associated ECN’s. The USB 3.0 device controller can optionally include an proprietary high-performance DMA engine for moving USB payloads. The register interface of the DMA engine is simple, allowing device-side class-specific function drivers to be implemented easily. Reference mass storage class device-side function drivers are also available to all licensees. All buffering associated with the DMA Engine are configurable based on latency and performance requirements.
The USB 3.0 device controller can include an proprietary EP0 processor block for managing all standard requests directed to the control endpoint, minimizing software development overheads. Class and vendor specific requests directed to the control endpoint are routed to the software via the DMA engine, for processing. Optionally, the controller can be provided with no DMA Engine and no buffering. This operates in a cut-through mode, forwarding and receiving USB payloads and managing only the USB protocol. In this case, the customer may implement their own differentiated DMA engine. A simple transmit and receive buffer is also included in this configuration which, accessible by software over the slave register access interface (typically AHB). This option results in very low-footprint hardware which can be used where the software can completely manage the USB traffic including USB transactions sequencing.
The USB 3.0 device controller can include an proprietary EP0 processor block for managing all standard requests directed to the control endpoint, minimizing software development overheads. Class and vendor specific requests directed to the control endpoint are routed to the software via the DMA engine, for processing. Optionally, the controller can be provided with no DMA Engine and no buffering. This operates in a cut-through mode, forwarding and receiving USB payloads and managing only the USB protocol. In this case, the customer may implement their own differentiated DMA engine. A simple transmit and receive buffer is also included in this configuration which, accessible by software over the slave register access interface (typically AHB). This option results in very low-footprint hardware which can be used where the software can completely manage the USB traffic including USB transactions sequencing.
Key features
- USB 3.0 Device controller can be configured to support all types of USB transfers – bulk, interrupt and isochronous.
- Allows dynamic configuration to support configurable number of endpoints, interfaces, alternate interfaces and configurations.
- USB 3.0 Device controller can be configured to support any combinations of USB 3.0 interface speeds – SSP (10 Gbps), SS (5 Gbps), HS (480 Mbps), FS (12 Mbps) and LS (1.5 Mbps). Sample combinations are SSP & SS only, SSP & SS & HS only, SSP & SS & HS & FS only, SS only, SS & HS only, SS & HS or FS only.
- USB 3.0 Device controller has full support for all low power features of the USB specification supporting suspend and remote wakeup, USB 3.0 low power states – U1/U2/U3 and USB 2.0 Link Power Management states – L1, L2.
- USB controllers have been silicon proven in wide range of products such as graphics controller, flash storage controllers, SATA bridges with support for bulk streaming, embedded hosts, docking stations, mobile application processors, smart TV, and hubs.
Block Diagram
USB 3.0 Device Controller IP block diagram
Benefits
- Highly modular and configurable design
- Layered architecture
- Fully synchronous design
- Supports both sync and async reset
- Clearly demarked clock domains
- Software control for key features
- Extensive clock gating support
- Multiple Power Well Support
Applications
- Graphics controller
- Flash storage controllers
- SATA bridges with support for bulk streaming
- Embedded hosts
- Docking stations
- Mobile application processors,
- Smart TV,
- Hubs
What’s Included?
- Configurable RTL code
- HDL-based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers, and performance monitors
- Configurable synthesis shell
- Design guide
- Verification guide
- Synthesis guide
- FPGA platform for pre-tape-out validation
- Reference firmware
Specifications
Identity
Part Number
USB 3.0 Device Controller IP
Vendor
T2M GmbH
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
T2M GmbH
T2M GmbH is the leading Global Technology Company supplying state of the art complex semiconductor connectivity IPs and KGDs, enabling the creation of complex connected devices for Mobile, IoT and Wearable markets.
T2M's unique SoC White Box IPs are the design database of mass production RF connectivity chips supporting standards including Wifi, BT, BLE, Zigbee, NFC, LTE, GSM, GNS. They are available in source code as well as KGD for SIP / modules.
With offices in USA, Europe, China, Taiwan, South Korea, Japan, Singapore and India, T2M’s highly experienced team provides local support, accelerating product development and Time 2 Market.
Learn more about USB IP core
Exploring USB Applications and the Impact of USB IP
Understanding USB IP and Its Role in SOC Integration
What Designers Need to Know About USB Low-Power States
In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond the basic features.
New USB 80Gbps Specification Boosts Data Rate, Enables Four Protocols on One Bus
Gervais Fong, Synopsys
New USB Device Class Specification Broadens Use Cases for I3C and I3C Basic
Sharmion Kerley, MIPI Alliance
Frequently asked questions about USB IP cores
What is USB 3.0 Gen1 / Gen2 Device Controller IP?
USB 3.0 Gen1 / Gen2 Device Controller IP is a USB IP core from T2M GmbH listed on Semi IP Hub.
How should engineers evaluate this USB?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.