Ultra-Small 8051-Compatible Microcontroller

The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers. The core integrates an 8051 CPU with a serial communication controller, flexible timer/counter, multi-purpose I/O port, interrupt controller, and optionally with a debug unit supporting JTAG and Single-Wire interfaces. 

The MCU executes some 8051 instructions in a single clock cycle, thus providing 0.1235 DMIPS/MHz (using the IAR Compiler) or 7.94x the performance per MHz of the original IntelTM 8051. Furthermore, the core can run at frequencies over 800MHz on a 40nm technology, offering performance that is almost 900x that of the original 8051. 

The T8051XC3 runs the legacy code of existing systems, but is also ready for highly productive new software development. This is facilitated through CAST’s on-chip debugging option, and debug pods that cooperate with the Keil μVision C51 and IAR Embedded Workbench for 8051 IDEs.
 
This T8051XC1 IP core builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. It is rigorously verified, scan-ready, and available in source-code RTL or targeted FPGA netlist. Designed for easy reuse in ASICs or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional module), synchronous/asynchronous reset (user-selectable), and no internal tristates.
 

• Fully compatible with the MCS®51 instruction set
• Compact silicon footprint:
  • CPU-Only: 4.0k Gates on 40nm
  • Complete MCU: 6.6k Gates on 40nm
• 0.1235 DMIPS/MHz or 7.94x more performance per MHz than the original Intel^TM 8051 with the IAR compiler
• Software Development
  • Supported by IAR Embedded Workbench^TM for 8051 and Keil μVision^TM C51 IDEs
  • JTAG-based or Single-Wire Serial Debug
  • Compatible with any MCS®51 compiler
• Interfaces and Peripherals
  • Special Function Registers interface
  • Up to 256B of internal data memory interface
  • External Memory Interface
    • Up to 64KB external program memory
    • Up to 64KB external data memory
  • Interrupt Controller with two or four priority levels, and eight interrupt sources
  • 8-bit Parallel I/O Port
  • Serial 0 full-duplex serial (UART) interface
  • Timer 1: Flexible timer/counter
  • On-Chip Debug Support (OCDS)
  • Power Management Unit with power-down modes (IDLE/STOP)
  • Other peripherals and extensions available upon request