Vendor: NTLab Category: Clock Generator

Programmable 9-bit CMOS frequency divider (2…511 dividing ratio)

The programmable CMOS frequency divider is a set of 8 serially connected dividers with the varied dividing ratio 2/3.

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Overview

The programmable CMOS frequency divider is a set of 8 serially connected dividers with the varied dividing ratio 2/3. This structure is especially effective for wide range of dividing ratio since the number of triggers to accomplish the specified ratio is minimized. The dividing ratio is 2…511.
Input frequency is 88...500 MHz.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.

Key features

  • iHP SGB25V
  • Range of dividing ratio 2…511
  • Maximum input frequency 500 MHz
  • Compact structure
  • Portable to other technologies (upon request)

Block Diagram

250iHP_NDIV_01 block diagram

Applications

  • PLL frequency synthesizer

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Specifications

Identity

Part Number
250iHP_NDIV_01
Vendor
NTLab
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab
HQ: Lithuania
NTLab is a vertically integrated microelectronics design center. It has 70+ experienced and qualified engineers. NTLab specializes in the designing of mixed-signal and RF ICs and Systems-on-Chip. It has a wide range of own silicon-verified IP blocks: processor cores, interfaces, analog and high-frequency PHYs, etc., thus allowing customized design to be fast and predictable. In-company unique combination of competences in digital, analog and RF circuits and embedded software enables NTLab to participate in the projects that require deep research and utilize most sophisticated and advanced techniques: multi-system GPS/GLONASS/Galileo/BeiDou/NavIC(IRNSS)/QZSS/SBAS navigation, RF ID, wireless communications, etc. All designed ICs are provided with test and development tools, as well as with reference software. NTLab offers a wide range of silicon proven analog/mixed-signal IPs in 0.35µm, 0.25 µm, 0.18 µm, 0.13 µm, 0.09 µm, 65nm, 55nm, 40nm, 28nm, 22 nm CMOS and SiGe BiCMOS processes. These IPs are suitable for devices targeted both consumer and industrial markets. Most of these IPs have been proven in silicon on the foundries: Samsung, UMC, GlobalFoundries, SMIC, VIS, Tower, X-FAB, iHP, AMS, SilTerra, STMicroelectronics, Winfoundry.
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Frequently asked questions about Clock Generator IP cores

What is Programmable 9-bit CMOS frequency divider (2…511 dividing ratio)?

Programmable 9-bit CMOS frequency divider (2…511 dividing ratio) is a Clock Generator IP core from NTLab listed on Semi IP Hub.

How should engineers evaluate this Clock Generator?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Clock Generator IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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