PDM Synthesizable Transactor
PDM Synthesizable Transactor provides a smart way to verify the PDM bus component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
PDM Synthesizable Transactor provides a smart way to verify the PDM bus component of a SOC or a ASIC in Emulator or FPGA platform.
Key features
- Full PDM Transmitter and Receiver functionality
- Supports 8,10,12,16,20,24,32 bit data precision
- Supports PDM modulator and PDM demodulator
- Supports PDM Digital output
- Supports PDM Error output
- PDM Verification IP comes with complete test suite to test every feature of PDM specification
- Supports fully synthesizable
- Supports static synchronous design
- Supports positive edge clocking and no internal tri-states
- Supports simple interface allows easy connection to microprocessor/microcontroller devices
Block Diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the PDM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about PDM IP cores
What is PDM Synthesizable Transactor?
PDM Synthesizable Transactor is a PDM IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this PDM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PDM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.